Advantech MIC-3393, User Manual

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MIC-3393 User Manual 70
C.2.3 General Purpose Registers
The general purpose registers are not related to any internal function of the FPGA
design. They hold the FPGA design revision IDs.
Name: MIN_REV
Address-Offset: 0x1C
H8 Address: 0xFFC01C
LPC Address: na
Name: MAJ_REV
Address-Offset: 0x1D
H8 Address: 0xFFC01D
LPC Address: 0x445
Bit Position Mnemonic Description
R/W (Type)
Default 0x
H8 LPC
7 : 0 MIN_REV
FPGA minor revision
This register holds the minor revi-
sion ID.
Minor revision changes are small
bug-fixes and improvements, which
have no influences to the FPGA
related firmware or application.
RO na 0
Bit Position Mnemonic Description R/W (Type) Default 0x
H8 LPC
7 : 0 MAJ_REV FPGA major revision This register
holds the major revision ID. Major
revision changes announcing design
changes and additions with impact to
the FPGA related firmware and
application.
RO RO 04