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MIC-3393 User Manual
Appendix C
F
PGA
Name:
FWH_SEL_ID
Address-Offset:
0x09
H8 Address:
0xFFC009
LPC Address:
0x446
Name:
SOL
Address-Offset:
na
H8 Address:
na
LPC Address:
0x449
Bit Position Mnemonic
Description
R/W (Type)
Defaul
t 0x
H8
LPC
7 : 4
Res
Reserved
RO
RO
0
3
BIOS_SWAP
'0' - IWD time out. BIOS swap to
golden BIOS.
'1' - IWD disable by BIOS read
0x446h. BIOS never swap.
RO
RO
1
2
Enable/Dis-
able D1
Bit D1 Function enable/disable
'0' - Bit D1 disabled, FWH_SEL_ID
can not be controlled by the value of
D1.
'1' - Bit D1 enabled, FWH_SEL_ID
can be controlled by the value of D1.
RO
RW
1
1
FWH_SEL_RE
G
FWH_SEL_ID control : Current flash
select (FWH_SEL_ID) is controlled
by the value of this bit if D2 is '1'.
RO
RW
1
0
FWH_SEL_ID
Status
Currently selected active
flash(FWH_SEL_ID) status
RO
RO
x
Bit Position Mnemonic
Description
R/W (Type)
Default 0x
H8
LPC
7 : 4
Res
Reserved
RO
RO
0
1
SOL_REG
SOL control : Current SOL UART
select
'0' - select SIO_UART1.
'1' - select SIO_UART2.
RO
RW
0
0
Enable/Dis-
able D1
Bit D1 Function enable/disable
'0' - Bit D1 disabled.
'1' - Bit D1 enabled.
RO
RW
0
Summary of Contents for MIC-3393
Page 1: ...User Manual MIC 3393 6U CompactPCI Intel Xeon Quad Dual Core Processor Blade...
Page 11: ...Chapter 1 1 Hardware Configuration This chapter describes how to configure MIC 3393 hardware...
Page 33: ...Chapter 2 2 AMI BIOS Setup This chapter describes how to configure the AMI BIOS...
Page 54: ...MIC 3393 User Manual 44 2 8 Advanced Chipset Settings Figure 2 22 Advanced chipset settings...
Page 59: ...Chapter 3 3 IPMI for the MIC 3393 This chapter describes IPMI con figuration for the MIC 3393...
Page 67: ...Appendix A A Pin Assignments This appendix describes pin assignments...
Page 75: ...Appendix C C FPGA This appendix describes FPGA configuration...
Page 83: ...Appendix D D Glossary...