Actel ProASIC3/E, User Manual, Page: 48 / 106

Quick Start Tutorial
48 ProASIC3/E Starter Kit User’s Guide and Tutorial
4. Select test_tbench.vhd in the Stimulus files in the project list box and click Add to add the file to the Associated
Files list.
5. Click OK . Stimulus icons in the Design flow window turn green to notify you that there is a testbench file associated
with them.
6. Click the Simulation icon in the Design Flow window, or right-click Top in the Design Hierarchy tab and select
Run Pre-Synthesis Simulation , as shown in Figure 7-22 .
Figure 7-22. Run Pre-Synthesis Simulation
The ModelSim VHDL simulator opens and compiles the source files, as shown in Figure 7-23 .
Figure 7-23. ModelSim Main Window
Once the compilation completes, the simulator simulates for the default time period of 1000 ns and a Wave window,
shown in
Figure 7-24 on page 49 , opens to display the simulation results.