Actel ProASIC3/E, User Manual, Page: 20 / 106

Hardware Components
20 ProASIC3/E Starter Kit User’s Guide and Tutorial
When the user of the evaluation board is in need of these BANK0 I/O lines of FPGA for his application, the shorting
links inserted on the 2-pin headers JP41, JP42, JP43, JP44, JP45, JP46, and JP47 are to be removed. Refer to
Figure B-
6 on page 87 . These BANK0 I/O lines of FPGA are also available on J14, J15, J16, and J17 for user evaluation.
Caution
Both the removal and insertion of shorting links on the JP41, JP42, JP43, JP44, JP45, JP46, and JP47 must be carried
out only when the entire PA3 evaluation board is in powered OFF condition.
Note: Using an R40 potentiometer, the contrast of letters displayed on the LCD can be varied.
LCD Power Supply Circuit
Power to the LCD module power supply is sourced from the LM2674M-5.0 switching regulator, which can provide up
to 500 mA.
Description
The MDLS-81809-SS-LV-G-LED-04-G LCD module requires a 5 V power supply. This is derived from VIN (DC
power jack J18). From VIN, which is at most 24 volts DC, the 5 volts required for the LCD module is derived using the
LM2674M-5.0 high efficiency 500 mA switching regulator U20.
The ON/OFF control required for the U20 is controlled by SW11.
Note: SW11 also controls U11 and hence all the board regulator power supplies.
The presence of the LCD power supply (5 V) from U20 is indicated by the LED D17. The glowing of D17 indicates
the presence of a 5 V power supply.
When the user of the PA3 evaluation board does not need the LCD at all, the shorting links on JP41, JP42, JP43, JP44,
JP45, JP46, and JP47 headers are to be removed. Follow the procedure listed in
“Caution” note on page 20 .
Refer to Figure B-11 on page 92 for the LCD power supply circuit details.
LVDS Channels
Four LVDS channels with up to a maximum signaling rate of 350 MHz are supported on the evaluation board. These
LVDS signals are brought out to a pair of RJ-45 (CAT-5E) sockets ( J40 and J41). Refer to the PA3 Evaluation board
PCB layout,
Figure 2-1 on page 10 , for the position of these connectors.
The LVDS signals are driven using 8 differential pairs (consisting of 16 I/O pins) from the west side (Bank6 and Bank7)
of the FPGA device A3PE600-PQ208. These 16 signals are terminated on the J40 and J41 connectors. The FPGA Pins
used for LVDS signaling are listed in
Table 2-4 on page 19 .
The LVDS signals are terminated on J40 and J41 connectors so that a standard patch cable can be used for doing loop-
back testing. Refer to
Figure 2-1 on page 10 of the PA3 evaluation board schematics for schematic representation of
connector signal details.