Actel ProASIC3/E, User Manual, Page: 29 / 106

ProASIC3/E Starter Kit User’s Guide and Tutorial 29
5
LVDS Signal Evaluation
Introduction
Due to concerns about the Proasic3 Dev-Kit board layout with respect to the LVDS signaling, the Applications
Consulting group took initiative to evaluate the LVDS signaling on the board. The performance criteria of the board
with respect to LVDS signaling is set to 300 Mb/s per product marketing.
This document explains the test setup and design. It reports the measurements performed on the board, and at the end,
makes recommendations to increase the LVDS signal quality in order to meet the performance criteria.
Test Setup
Hardware
The test setup uses a ProASIC3 Dev-Kit containing an A3PE600-PQ208 engineering sample. LVDS loopback is
closed using various lengths of CAT-5E cables (1-, 3-, and 6-foot). The measurements are taken using a 1159A-1GHz
Agilent differential probe.
Design
Figure 5-1 on page 29 shows the block diagram of the transmitter section of the test design programmed inside the
Proasic3 FPGA. As shown in Figure 5-1 on page 29 , the design contains two similar channels of data. One channel
(channel A) is driven by PLL to achieve high data rates, and the other (channel B) uses an external clock in case slow
data rates are needed for test or debugging purposes.
Figure 5-1. TX Portion of Test Design
Each channel uses an LFSR to generate a pseudo-random data stream. The data stream is entered in DDR registers to
achieve higher data rates from relatively slower clocks (e.g., 300 Mb/s data rate from 150 MHz clock). The output of the
DDR registers is sent out using the LVDS I/O standard. The output data is looped back and received by the FPGA
using LVDS receivers.
PLL
LFSR_1
clk
out
clk
LFSR_2
out
DDR-REG
Qf
Qr
Clk
Dout
LFSR_1
clk
out
clk
LFSR_2
out
DDR-REG
Qf
Qr
Clk
Dout
CLK_1
CLK_2
Channel A
Channel B