Actel ProASIC3/E, User Manual, Page: 35 / 106

ProASIC3/E Starter Kit User’s Guide and Tutorial 35
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Quick Start Tutorial
This tutorial illustrates a VHDL design for a ProASIC3/E starter kit board. The design is created in Actel Libero IDE
v6.2. The steps involved are as follows:
“Step 1 – Create a New Project”
“Step 2 – Perform Pre-Synthesis Simulation”
“Step 3 – Synthesize the Design in Synplify”
“Step 4 – Perform Post-Synthesis Simulation”
“Step 5 – Implement the Design with Designer”
“Step 6 – Perform Timing Simulation with Back-Annotated Timing”
“Step 7 – Generate the Programming File”
“Step 8 – Program the Device”
Step 1 – Create a New Project
This step uses the Libero IDE HDL Editor to enter an Actel VHDL design.
To create the VHDL project:
1. Double-click the Libero IDE icon on your desktop to start the program.
2. From the File menu, select New Project . This displays the New Project Wizard, as shown in Figure 7-1 .
Figure 7-1. New Project Wizard in Libero IDE
3. Enter your Project name . For this tutorial, name your project quickstart .
4. Select your HDL type.
5. If necessary, in the Project location field, click Browse to navigate to C:\Actelprj. Click Next to continue.