Actel ProASIC3/E, User Manual, Page: 22 / 106

Hardware Components
22 ProASIC3/E Starter Kit User’s Guide and Tutorial
Also note that the V
CCI
and VMV voltages of Bank6 and Bank7 (west side) are connected to a fixed 2.5 volts, which is
required in ProASIC3 (LVDS only available in A3P250 and larger) and ProASIC3E (LVDS available in all devices) for
LVDS signaling.
Refer to the PCB layout, Figure 2-1 on page 10 , for the location of J40 and J41 connectors on the PA3 Evaluation board.
Table 2-7 · FPGA – LVDS I/O Pin Details
FPGA Pin No. FPGA I/O Pin Name
1
Signal Name
CAT5E
Connector
Pin No.
7 GAC2/IO132PDB7V1 TX1+ CAT 5E – PRI –1
8 IO132NDB7V1 TX1– CAT 5E – PRI –2
9 IO130PDB7V1 TX2+ CAT 5E – PRI – 5
10 IO130NDB7V1 TX2– CAT 5E – PRI – 4
11 IO127PDB7V1 RX1+ CAT 5E – PRI –3
12 IO127NDB7V1 RX1– CAT 5E – PRI – 6
13 IO126PDB7V0 RX2+ CAT 5E – PRI – 7
14 IO126NDB7V0 RX2– CAT 5E – PRI – 8
30 GFA2/IO117PDB6V1 TX3+ CAT 5E – SEC –3
31 IO117NDB6V1 TX3– CAT 5E – SEC –6
37 IO112PDB6V1 TX4+ CAT 5E – SEC – 7
38 IO112NDB6V1 TX4– CAT 5E – SEC – 8
42 IO106PDB6VO RX3+ CAT 5E – SEC –1
43 IO106NDB6V0 RX3– CAT 5E – SEC – 2
44 GEC1/IO104PDB6V0 RX4+ CAT 5E – SEC – 5
45 GEC0/IO104NDB6VO RX4– CAT 5E – SEC – 4
Notes:
1. Pin names are valid only for the A3PE600-PQ208 part. They are not correct for use with an
A3P250.
2. J40 – RJ45 connector is referred as CAT 5E PRIMARY connector.
3. J41 – RJ45 connector is referred as CAT 5E SECONDARY connector