Actel ProASIC3/E, User Manual, Page: 39 / 106

Step 1 – Create a New Project
ProASIC3/E Starter Kit User’s Guide and Tutorial 39
To add HDL to your project:
1. From the File menu, click New . This opens the New dialog box, as shown in Figure 7-8 .
Figure 7-8. New File Dialog Box
2. Select VHDL Entity in the File Type field, enter count8 in the Name field, and click OK . The HDL Editor opens.
Enter the following VHDL file, or if this document is open in an electronic form, copy and paste it from here.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity count8 is
port(Clock : in std_logic;
Q : out std_logic_vector(7 downto 0);
Updown : in std_logic;
Aclr : in std_logic;
Sload : in std_logic;
Data : in std_logic_vector(7 downto 0));
end count8;
architecture behavioral of count8 is
signal Qaux : UNSIGNED(7 downto 0);
begin
process(Clock, Aclr)
begin
if (Aclr = '1') then
Qaux <= (others => '0');