Abov MC96F6432A User Manual Download

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MC96F6432A

ABOV Semiconductor Co., Ltd.

11.12.20.2

USIn I2C Master Receiver

To operate I2C in master receiver, follow the recommended steps below.

Enable I2C by setting USInMS[1:0]bits in USInCR1 and USInEN bit in USInCR2. This provides main clock to

the peripheral.

Load SLAn+R into the USInDR where SLA is address of slave device and R is transfer direction from the

viewpoint of the master. For master receiver, R is

‘1’. Note that USInDR is used for both address and data.

Configure baud rate by writing desired value to both USInSCLR and USInSCHR for the Low and High period

of SCLn line.

Configure the USInSDHR to decide when SDAn changes value from falling edge of SCLn. If SDAn should

change in the middle of SCLn LOW period, load half the value of USInSCLR to the USInSDHR.

Set the STARTCn bit in USInCR4. This transmits a START condition. And also configure how to handle

interrupt and ACK signal. When the STARTCn bit is set, 8-bit data in USInDR is transmitted out according to

the baud-rate.

This is ACK signal processing stage for address packet transmitted by master. When 7-bit address and 1-bit

transfer direction is transmitted to target slave device, the master can know whether the slave acknowledged

or not in the 9

high period of SCLn. If the master gains bus mastership, I2C generates GCALL interrupt

regardless of the reception of ACK from the slave device. When I2C loses bus mastership during arbitration

process, the MLOSTn bit in USInST2 is set and I2C waits in idle state or can be operate as an addressed

slave. To operate as a slave when the MLOSTn bit in USInST2 is set, the ACKnEN bit in USInCR4 must be

set and the received 7-bit address must equal to the USInSLA[6:0] bits in USInSAR. In this case I2C

operates as a slave transmitter or a slave receiver (go to appropriate section). In this stage, I2C holds the

SCLn LOW. This is because to decide whether I2C continues serial transfer or stops communication. The

following steps continue assuming that I2C does not lose mastership during first data transfer.

I2C (Master) can choose one of the following cases according to the reception of ACK signal from slave.

1) Master receives ACK signal from slave, so continues data transfer because slave can prepare and

transmit more data to master. Configure ACKnEN bit in USInCR4 to decide whether I2C ACKnowledges the

next data to be received or not.

2) Master stops data transfer because it receives no ACK signal from slave. In this case, set the STOPCn bit

in USInCR4.

3) Master transmits repeated START condition due to no ACK signal from slave. In this case, load

SLAn+R/W into the USInDR and set STARTCn bit in USInCR4.

After doing one of the actions above, clear to

“0b” all interrupt source bits in USInST2 to release SCLn line. In

case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to

step 6 after transmitting the data in USInDR and if transfer direction bit is

‘0’ go to master transmitter section.

Summary of Contents for MC96F6432A

Page 1: ...tect Reset Internal 16MHz RC Oscillator 1 5 TA 0 50 C Watchdog Timer RC Oscillator 5kHz Peripheral Features 12 bit Analog to Digital Converter 16 inputs USI USART SPI I2C 2 sets LCD Driver 21 segments x 8 commons I O and Packages Up to 42 programmable I O lines with 48 44 pin package 48 QFN 44 MQFP 32 LQFP 32 28 SOP Operating Conditions 2 2V to 5 5V Wide Voltage Range 40 C to 85 C Temperature Rang...

Page 2: ...Frequency in Electrical Characteristics 1 4 2016 05 30 Add a MC96F6332AL 32LQFP package 1 5 2016 07 06 Remove the 28TSSOP package Change Gang programmer from StandAlone GANG8 to E GANG4 E GANG6 Fixed typos of I2C Status Register 1 6 2017 02 09 Revised this book Updated Package diagrams in Chapter 4 Package Diagram Added the note on the flash memory erase and write in Chapter 15 Flash Memory Update...

Page 3: ... interval timer watchdog timer 8 16 bit timer counter 16 bit PPG output 8 bit PWM output 10 bit PWM output watch timer buzzer driving port SPI USI 12 bit A D converter LCD driver on chip POR LVR LVI on chip oscillator and clock circuitry The MC96F6432A also supports power saving modes to reduce power consumption Device Name FLASH XRAM IRAM ADC I O PORT Package MC96F6432AU 32Kbytes 768bytes 256byte...

Page 4: ...21segments and 8common terminals Internal or external resistor bias Two Internal Resistors Selectable 1 2 1 3 1 4 1 5 1 6 and 1 8 duty selectable Resistor Bias and 16 step contrast control Power On Reset Reset release level 1 4V Low Voltage Reset 12 levels detect 1 85 2 20 2 32 2 44 2 59 2 75 2 93 3 14 3 38 3 67 4 00 4 40V Low Voltage Indicator 11 levels detect 2 20 2 32 2 44 2 59 2 75 2 93 3 14 3...

Page 5: ... or change the value of MCU internal memory and I O peripherals And the OCD also controls MCU internal debugging logic it means OCD controls emulation step run monitoring etc The OCD debugger program works on Microsoft Windows NT 2000 XP Vista 32 bit operating system If you want to see more details please refer to OCD debugger manual You can download debugger S W and manual from our web site http ...

Page 6: ...BFFH Address 0100H 0FFFH Address 0100H 77FFH Address 0100H 7BFFH Address 0100H 7DFFH Address 0100H 7EFFH 4 kinds of protection size selectable Address 0100H 0FFFH Address 0100H 07FFH Address 0100H 03FFH Address 0100H 01FFH 4 kinds of protection size selectable Address 0100H 0FFFH Address 0100H 07FFH Address 0100H 03FFH Address 0100H 01FFH ADC A D Converter INL 6LSB DNL 1 LSB TOE 5 LSB ZOE 5 LSB A ...

Page 7: ...7 MC96F6432A ABOV Semiconductor Co Ltd 1 3 3 Programmer Single programmer E PGM It programs MCU device directly DSDA VDD DSCL VSS Figure 1 2 E PGM Single writer ...

Page 8: ...tor Co Ltd Gang programmer E GANG4 and E GANG6 It can run PC controlled mode It can run standalone without PC control too USB interface is supported Easy to connect to the handler Figure 1 3 E GANG4 and E GANG6 for Mass Production ...

Page 9: ...signal lines are ready at the PCB of application board is designed 1 4 2 1 Circuit Design Guide At the FLASH programming the programming tool needs 4 signal lines that are DSCL DSDA VDD and VSS When you design the PCB circuits you should consider the usage of these signal lines for the on board programming Please be careful to design the related circuit of these signal pins because rising falling ...

Page 10: ...ovided to pin DSCL and DSDA And it will cause some damages to the application circuits connected to DSCL or DSDA port if the application circuit is designed as high speed response such as relay control circuit If possible the I O configuration of DSDA DSCL pins had better be set to input mode 2 The value of R1 and R2 is recommended value It varies with circuit of system Figure 1 4 PCB design guide...

Page 11: ...768kHz Crystal OSC LCD driver 21 segments Buzzer 1 channel 8 bit UART 2 channels 8 bit SPI 3 channels 8 bit I2C 2 channels 8 bit CORE M8051 General purpose I O 9 ports normal I O 33 ports LCD shared I O Watchdog timer 1 channel 8 bit 5kHz internal RC OSC Basic interval timer 1 channel 8 bit Timer Counter 1 channel 8 bit 2 channels 16 bit 2 channels 8 bit or 1 channel 16 bit ADC 16 Input channels 1...

Page 12: ...8 MISO2 P16 SEG20 AN7 EINT7 SCK2 P13 SEG17 AN10 EC1 BUZO P14 SEG18 AN9 MOSI2 P06 SEG23 AN4 EINT4 PWM4CA P25 SEG8 P24 SEG9 P23 SEG10 P22 SEG11 SS1 P21 SEG12 AN15 SCK1 P20 SEG13 AN14 TXD1 SDA1 MOSI1 P10 SEG14 AN13 RXD1 SCL1 MISO1 P27 SEG6 P26 SEG7 P31 COM6 SEG4 P30 COM7 SEG5 P51 XIN P50 XOUT P02 AN0 AVREF EINT0 T4O PWM4AA P01 T3O DSCL P00 EC3 DSDA VDD P03 SEG26 AN1 EINT1 PWM4AB VSS P32 COM5 SEG3 P33...

Page 13: ... P07 SEG22 AN5 EINT5 PWM4CB P15 SEG19 AN8 MISO2 P16 SEG20 AN7 EINT7 SCK2 P13 SEG17 AN10 EC1 BUZO P14 SEG18 AN9 MOSI2 P06 SEG23 AN4 EINT4 PWM4CA P25 SEG8 P24 SEG9 P23 SEG10 P22 SEG11 SS1 P21 SEG12 AN15 SCK1 P20 SEG13 AN14 TXD1 SDA1 MOSI1 P10 SEG14 AN13 RXD1 SCL1 MISO1 P27 SEG6 P26 SEG7 P31 COM6 SEG4 P30 COM7 SEG5 P51 XIN P50 XOUT P02 AN0 AVREF EINT0 T4O PWM4AA P01 T3O DSCL P00 EC3 DSDA VDD P03 SEG2...

Page 14: ...A P22 SEG11 SS1 P21 SEG12 AN15 SCK1 P20 SEG13 AN14 TXD1 SDA1 MOSI1 P10 SEG14 AN13 RXD1 SCL1 MISO1 P27 SEG6 P26 SEG7 P31 COM6 SEG4 P30 COM7 SEG5 P51 XIN P50 XOUT P02 AN0 AVREF EINT0 T4O PWM4AA P01 T3O DSCL P00 EC3 DSDA VDD VSS P32 COM5 SEG3 P33 COM4 SEG2 P42 VLC1 SCK0 P53 SXIN T0O PWM0O P54 SXOUT EINT10 P03 SEG26 AN1 EINT1 PWM4AB NOTE 1 The programmer E PGM E Gang4 E Gang6 uses P0 1 0 pin as DSCL D...

Page 15: ...ted as a push pull output or an input with pull up resistor by software control when the 32 pin package is used Figure 3 4 MC96F6332AD 32SOP pin assignment 1 2 13 14 8 9 10 11 12 3 4 5 6 7 16 15 21 20 19 18 17 26 25 24 23 22 28 27 P51 XIN P52 EINT8 EC0 BLNK P53 SXIN T0O PWM0O P54 SXOUT EINT10 VSS P50 XOUT P55 RESETB P40 VLC3 RXD0 SCL0 MISO0 P41 VLC2 TXD0 SDA0 MOSI0 P32 COM5 SEG3 P31 COM6 SEG4 P30 ...

Page 16: ...16 MC96F6432A ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 48 Pin QFN Package ...

Page 17: ...17 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 2 44 Pin MQFP Package ...

Page 18: ...18 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 3 32 Pin LQFP Package ...

Page 19: ...19 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 4 32 Pin SOP Package ...

Page 20: ...20 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 5 28 Pin SOP Package ...

Page 21: ...4 SEG18 AN9 MOSI2 P15 SEG19 AN8 MISO2 P16 SEG20 AN7 EINT7 SCK2 P17 SEG21 AN6 EINT6 SS2 P20 I O Port 2 is a bit programmable I O port which can be configured as an input a push pull output or an open drain output A pull up resistor can be specified in 1 bit unit The P23 P25 are not in the 32 pin package The P22 P27 are not in the 28 pin package Input SEG13 AN14 TXD1 SDA1 MOSI1 P21 SEG12 AN15 SCK1 P...

Page 22: ...nput Input P12 SEG16 AN11 T1O PWM1O EINT12 I O External interrupt input and Timer 2 capture input Input P11 SEG15 AN12 T2O PWM2O T0O I O Timer 0 interval output Input P53 SXIN PWM0O T1O I O Timer 1 interval output Input P12 SEG16 AN11 EINT11 PWM1O T2O I O Timer 2 interval output Input P11 SEG15 AN12 EINT12 PWM2O T3O I O Timer 3 interval output Input P01 DSCL T4O I O Timer 4 interval output Input P...

Page 23: ... EINT6 TXD0 I O UART 0 data output Input P41 VLC2 SDA0 MOSI0 TXD1 I O UART 1 data output Input P20 SEG13 AN14 SDA1 MOSI1 RXD0 I O UART 0 data input Input P40 VLC3 SCL0 MISO0 RXD1 I O UART 1 data input Input P10 SEG14 AN13 SCL1 MISO1 SCL0 I O I2C 0 clock input output Input P40 VLC3 RXD0 MISO0 SCL1 I O I2C 1 clock input output Input P10 SEG14 AN13 RXD1 MISO1 SDA0 I O I2C 0 data input output Input P4...

Page 24: ...gnal outputs Input P35 P34 COM2 COM3 SEG2 SEG5 P33 P30 COM4 COM7 SEG6 SEG10 P27 P23 SEG11 P22 SS1 SEG12 P21 SCK1 AN15 SEG13 P20 AN14 TXD1 SDA1 MOSI1 SEG14 P10 AN13 RXD1 SCL1 MISO1 SEG15 P11 AN12 EINT12 T2O PWM2O SEG16 P12 AN11 EINT11 T1O PWM1O SEG17 P13 AN10 EC1 SEG18 P14 AN9 MOSI2 SEG19 P15 AN8 MISO2 SEG20 P16 AN7 EINT7 SCK2 SEG21 P17 AN6 EINT6 SS2 SEG22 P07 AN5 EINT5 PWM4CB SEG23 P06 AN4 EINT4 P...

Page 25: ...Description conclude NOTE 1 The P14 P17 P23 P25 P34 P37 and P43 are not in the 32 pin package 2 The P13 P17 P22 P27 P34 P37 and P43 are not in the 28 pin package 3 The P55 RESETB pin is configured as one of the P55 and RESETB pin by the CONFIGURE OPTION 4 If the P00 EC3 DSDA and P01 T3O DSCL pins are connected to the programmer during power on reset the pins are automatically configured as In syst...

Page 26: ... VDD OPEN DRAIN REGISTER DATA REGISTER DIRECTION REGISTER MUX 0 1 MUX 1 0 CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT PORTx INPUT or SUB FUNC DATA INPUT SUB FUNC DIRECTION SUB FUNC ENABLE SUB FUNC DATA OUTPUT Level Shift ExtVDD to 1 8V Level Shift 1 8V to ExtVDD Figure 6 1 General Purpose I O Port ...

Page 27: ... 1 0 INTERRUPT ENABLE EXTERNAL INTERRUPT Q D CP r VDD FLAG CLEAR POLARITY REG MUX 1 0 DEBOUNCE ENABLE Q D CP r DEBOUNCE CLK CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT PORTx INPUT or SUB FUNC DATA INPUT SUB FUNC DIRECTION SUB FUNC ENABLE SUB FUNC DATA OUTPUT Level Shift ExtVDD to 1 8V Level Shift 1 8V to ExtVDD Figure 6 2 External Interrupt I O Port ...

Page 28: ...tings NOTE 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at any other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 7 2 Reco...

Page 29: ...AIN AVREF 5 12V 2 uA ADC Operating Current IADC Enable VDD 5 12V 1 2 mA Disable 0 1 uA Table 7 3 A D Converter Characteristics NOTE 1 Zero offset error is the difference between 000000000000 and the converted output for zero input voltage VSS 2 Full scale error is the difference between 111111111111 and the converted output for full scale input voltage AVREF 3 When AVREF is lower than 2 7V the ADC...

Page 30: ...150 mV Minimum Pulse Width tLW 100 us LVR and LVI Current IBL Enable Both VDD 3V RUN Mode 14 0 24 0 uA Enable One of two 10 0 18 0 Disable Both VDD 3V 0 1 Table 7 5 LVR and LVI Characteristics 7 6 High Internal RC Oscillator Characteristics TA 40 C 85 C VDD 2 2V 5 5V VSS 0V Parameter Symbol Conditions MIN TYP MAX Unit Frequency fIRC VDD 2 2 5 5V 16 MHz Tolerance TA 0 C to 50 C With 0 1uF Bypass ca...

Page 31: ...CDCCR 00H Typx0 9 VDDx16 31 Typx1 1 V LCDCCR 01H VDDx16 30 LCDCCR 02H VDDx16 29 LCDCCR 03H VDDx16 28 LCDCCR 04H VDDx16 27 LCDCCR 05H VDDx16 26 LCDCCR 06H VDDx16 25 LCDCCR 07H VDDx16 24 LCDCCR 08H VDDx16 23 LCDCCR 09H VDDx16 22 LCDCCR 0AH VDDx16 21 LCDCCR 0BH VDDx16 20 LCDCCR 0CH VDDx16 19 LCDCCR 0DH VDDx16 18 LCDCCR 0EH VDDx16 17 LCDCCR 0FH VDDx16 16 LCD Mid Bias Voltage note VLC1 VDD 2 7V to 5 5V...

Page 32: ... TA 25 C RESETB VDD 5 0V 150 250 400 kΩ VDD 3 0V 300 500 700 OSC feedback resistor RX1 XIN VDD XOUT VSS TA 25 C VDD 5V 600 1200 2000 kΩ RX2 SXIN VDD SXOUT VSS TA 25 C VDD 5V 2500 5000 10000 Supply Current IDD1 RUN fXIN 8MHz VDD 5V 10 2 6 5 2 mA fXIN 4MHz VDD 3V 10 1 2 2 4 fIRC 16MHz VDD 5V 10 3 0 6 0 IDD2 IDLE fXIN 8MHz VDD 5V 10 1 8 3 6 mA fXIN 4MHz VDD 3V 10 0 8 1 6 fIRC 16MHz VDD 5V 10 1 5 3 0 ...

Page 33: ... 5V 10 us Interrupt Input High Low Width tIWH tIWL All interrupt VDD 5V 200 ns External Counter Input High Low Pulse Width tECWH tECWL ECn VDD 5V n 0 1 3 200 External Counter Transition Time tREC tFEC ECn VDD 5V n 0 1 3 20 Table 7 10 AC Characteristics tIWH tIWL External Interrupt tRST 0 2VDD 0 2VDD 0 8VDD RESETB tECWH tECWL ECn 0 2VDD 0 8VDD tFEC tREC Figure 7 1 AC Timing ...

Page 34: ...L Internal SCK source 70 Input Clock High Low Pulse Width External SCK source 70 First Output Clock Delay Time tFOD Internal External SCK source 100 Output Clock Delay Time tDS 50 Input Setup Time tDIS 100 Input Hold Time tDIH 150 Table 7 11 SPI0 1 2 Characteristics SSn Output Input SCKn CPOLn 0 Output Input SCKn CPOLn 1 Output Input MISOn MOSIn Data Input tFOD tSCK tSCKL tSCKH 0 8VDD 0 2VDD MSB L...

Page 35: ...input data valid tS2 590 Output data hold after clock rising edge tH1 tCPU 50 tCPU Input data hold after clock rising edge tH2 0 Serial port clock High Low level width tHIGH tLOW 720 tCPU 8 1280 Table 7 12 UART0 1 Characteristics tHIGH tLOW tSCK Figure 7 3 Waveform for UART0 1 Timing Characteristics Shift Clock Data Out D1 D2 D3 D4 D5 D6 D7 D0 Valid Data In Valid Valid Valid Valid Valid Valid Vali...

Page 36: ... tSCLL 4 7 1 3 Bus Free Time tBF 4 7 1 3 Start Condition Setup Time tSTSU 4 7 0 6 Start Condition Hold Time tSTHD 4 0 0 6 Stop Condition Setup Time tSPSU 4 0 0 6 Stop Condition Hold Time tSPHD 4 0 0 6 Output Valid from Clock tVD 0 0 Data Input Hold Time tDIH 0 0 1 0 Data Input Setup Time tDIS 250 100 ns Table 7 13 I2C0 1 Characteristics SCLn SDAn tSTSU tSTHD SDAn Out tSCLH tSCLL tDIH tDIS tVD tVD ...

Page 37: ...imer Active VDD NOTE tWAIT is the same as the selected bit overflow of BIT X 1 BIT Clock INT Request Execution of STOP Instruction Data Retention Stop Mode Normal Operating Mode 0 8VDD tWAIT VDDDR Figure 7 6 Stop Mode Release Timing when Initiated by an Interrupt NOTE tWAIT is the same as 4096 X 4 X 1 fx 16 4ms 1MHz VDD RESETB Execution of STOP Instruction Data Retention Stop Mode Oscillation Stab...

Page 38: ...ndurance of Write Erase NFWE Sector 0 to 507 10 000 times Sector 508 to 511 256 bytes 100 000 Flash Data Retention Time tRT 10 years Table 7 15 Internal Flash Rom Characteristics NOTE 1 During a flash operation SCLK 1 0 of SCCR must be set to 00 or 01 INT RC OSC or Main X TAL for system clock 7 16 Input Output Capacitance TA 40 C 85 C VDD 0V Parameter Symbol Condition MIN TYP MAX Unit Input Capaci...

Page 39: ...tion frequency 2 2V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 8 5 Ceramic Oscillator Main oscillation frequency 2 2V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 8 5 External Clock XIN input frequency 2 2V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 8 5 Table 7 17 Main Clock Oscillator Characteristics XIN XOUT C1 C2 Figure 7 8 Crystal Ceramic Oscillator XIN XOUT External Clock Source Open Figure 7 9 External Clock ...

Page 40: ...illator Parameter Condition MIN TYP MAX Unit Crystal Sub oscillation frequency 2 2V 5 5V 32 32 768 38 kHz External Clock SXIN input frequency 32 100 kHz Table 7 18 Sub Clock Oscillator Characteristics SXIN SXOUT C1 C2 Figure 7 10 Crystal Oscillator SXIN SXOUT External Clock Source Open Figure 7 11 External Clock ...

Page 41: ...gh and low width tXH tXL 58 1250 ns Table 7 19 Main Oscillation Stabilization Characteristics tXH tXL XIN 0 2VDD 0 8VDD 1 fXIN Figure 7 12 Clock Timing Measurement at XIN 7 20 Sub Oscillation Characteristics TA 40 C 85 C VDD 2 2V 5 5V Oscillator Parameter MIN TYP MAX Unit Crystal 10 s External Clock SXIN input high and low width tXH tXL 5 15 us Table 7 20 Sub Oscillation Stabilization Characterist...

Page 42: ...A ABOV Semiconductor Co Ltd 7 21 Operating Voltage Range 2 2 0 4MHz 2 7 5 5 8 5MHz fXIN 0 4 to 8 5MHz Supply voltage V 4 2MHz 2 2 5 5 32 768kHz Supply voltage V fSUB 32 to 38kHz Figure 7 14 Operating Voltage Range ...

Page 43: ...ively for noise immunity X tal SXOUT SXIN 32 768kHz The main and sub crystal should be within 1cm from the pins of MCU on the PCB layout 0 1uF VDD VCC The MCU power line VDD and VSS should be separated from the high current part at a DC power node on the PCB layout DC Power The load capacitors of the sub clock C1 C2 CL x 2 15 CL C1 x C2 C1 C2 Cstray CL the specific capacitor value of crystal Cstra...

Page 44: ...Ω Recommended C2 47uF 25V more The R1 and C2 should be as close by the C3 as possible 3 The C3 capacitor is used for temperature compensation because an electrolytic capacitor becomes worse characteristics at low temperature Recommended C3 ceramic capacitor 2 2uF more The C3 should be within 1cm from VDD pin of MCU on the PCB layout 4 The above circuit is recommended to improve noise immunity EFT ...

Page 45: ...te properly only within the specified range The data presented in this section is a statistical summary of data collected on units from different lots over a period of time Typical represents the mean of the distribution while max or min represents mean 3σ and mean 3σ respectively where σ is standard deviation Figure 7 17 RUN IDD1 Current Figure 7 18 IDLE IDD2 Current 0 00 0 50 1 00 1 50 2 00 2 50...

Page 46: ...ductor Co Ltd Figure 7 19 SUB RUN IDD3 Current Figure 7 20 SUB IDLE IDD4 Current 0 0 20 0 40 0 60 0 80 0 100 0 120 0 2 5 3 0 3 5 4 5 5 0 5 5 25 C 85 C 40 C 0 0 5 0 10 0 15 0 20 0 25 0 30 0 2 5 3 0 3 5 4 5 5 0 5 5 25 C 85 C 40 C ...

Page 47: ...47 MC96F6432A ABOV Semiconductor Co Ltd Figure 7 21 STOP IDD5 Current 0 0 0 5 1 0 1 5 2 0 2 5 2 5 3 0 3 5 4 5 5 0 5 5 25 C 85 C 40 C ...

Page 48: ... counter is capable of addressing up to 64 Kbytes but this device has just 32 Kbytes as program memory space Figure 8 1 shows the map of the lower part of the program memory After reset the CPU begins execution from address 0000H Each interrupt is assigned to a fixed address in program memory The interrupt causes the CPU to jump to that address where it commences execution of the service routine E...

Page 49: ...49 MC96F6432A ABOV Semiconductor Co Ltd FFFFH 0000H 32Kbytes 7FFFH Figure 8 1 Program Memory NOTE 1 32Kbytes Including Interrupt Vector address ...

Page 50: ...ying the same block of addresses 80H through FFH although they are physically separate entities The lower 128 bytes of RAM are present in all 8051 devices as mapped in Figure 8 3 The lowest 32 bytes are grouped into 4 banks of 8 registers Program instructions call out these registers as R0 through R7 Two bits in the Program Status Word select which register bank is in use This allows more efficien...

Page 51: ... 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 80bytes 16bytes 128bits 8bytes 8bytes 8bytes 8bytes Register Bank 3 8bytes Register Bank 2 8bytes Register Bank 1 8by...

Page 52: ...XSFR This area has no relation with RAM FLASH It can be read and written to through SFR with 8 bit unit External RAM 768bytes Indirect Addressing LCD Display RAM 0000H 001AH 001BH 02FFH 107FH 1000H Extended Special Function Registers 128bytes Indirect Addressing Not used Figure 8 4 XDATA Memory Area ...

Page 53: ...P15DB 0D0H PSW P5IO P0FSRL P0FSRH P1FSRL P1FSRH P2FSRL P2FSRH 0C8H OSCCR P4IO 0C0H EIFLAG0 P3IO T2CRL T2CRH T2ADRL T2ADRH T2BDRL T2BDRH 0B8H IP P2IO T1CRL T1CRH T1ADRL T1ADRH T1BDRL T1BDRH 0B0H P5 P1IO T0CR T0CNT T0DR T0CDR SPICR SPIDR SPISR 0A8H IE IE1 IE2 IE3 P0PU P1PU P2PU P3PU 0A0H P4 P0IO EO P4PU EIPOL0L EIPOL0H EIFLAG1 EIPOL1 98H P3 LCDCRL LCDCRH LCDCCR ADCCRL ADCCRH ADCDRL ADCDRH 90H P2 P0O...

Page 54: ...H 07H 0FH 1078H 1070H 1068H 1060H 1058H 1050H 1048H 1040H 1038H XTFLSR 1030H 1028H 1020H 1018H 1010H T4DLYA T4DLYB T4DLYC T4DR T4CAPR T4CNT 1008H T4PPRL T4PPRH T4ADRL T4ADRH T4BDRL T4BDRH T4CDRL T4CDRH 1000H T3CR T3CNT T3DR T3CAPR T4CR T4PCR1 T4PCR2 T4PCR3 T4ISR T4IMSK Table 8 2 XSFR Map Summary ...

Page 55: ... 8EH Watch Dog Timer Data Register WDTDR W 1 1 1 1 1 1 1 1 Watch Dog Timer Counter Register WDTCNT R 0 0 0 0 0 0 0 0 8FH BUZZER Data Register BUZDR R W 1 1 1 1 1 1 1 1 90H P2 Data Register P2 R W 0 0 0 0 0 0 0 0 91H P0 Open drain Selection Register P0OD R W 0 0 0 0 0 0 0 0 92H P1 Open drain Selection Register P1OD R W 0 0 0 0 0 0 0 0 93H P2 Open drain Selection Register P2OD R W 0 0 0 0 0 0 0 0 94...

Page 56: ... P1PU R W 0 0 0 0 0 0 0 0 AEH P2 Pull up Resistor Selection Register P2PU R W 0 0 0 0 0 0 0 0 AFH P3 Pull up Resistor Selection Register P3PU R W 0 0 0 0 0 0 0 0 B0H P5 Data Register P5 R W 0 0 0 0 0 0 B1H P1 Direction Register P1IO R W 0 0 0 0 0 0 0 0 B2H Timer 0 Control Register T0CR R W 0 0 0 0 0 0 0 B3H Timer 0 Counter Register T0CNT R 0 0 0 0 0 0 0 0 B4H Timer 0 Data Register T0DR R W 1 1 1 1...

Page 57: ... Word Register PSW R W 0 0 0 0 0 0 0 0 D1H P5 Direction Register P5IO R W 0 0 0 0 0 0 D2H P0 Function Selection Low Register P0FSRL R W 0 0 0 0 0 0 0 D3H P0 Function Selection High Register P0FSRH R W 0 0 0 0 0 0 D4H P1 Function Selection Low Register P1FSRL R W 0 0 0 0 0 0 0 0 D5H P1 Function Selection High Register P1FSRH R W 0 0 0 0 0 0 0 0 D6H P2 Function Selection Low Register P2FSRL R W 0 0 ...

Page 58: ...USI1SAR R W 0 0 0 0 0 0 0 0 EEH P3 Function Selection Register P3FSR R W 0 0 0 0 0 0 0 0 EFH P4 Function Selection Register P4FSR R W 0 0 0 0 0 0 0 F0H B Register B R W 0 0 0 0 0 0 0 0 F1H USI1 Status Register 1 USI1ST1 R W 1 0 0 0 0 0 0 F2H USI1 Status Register 2 USI1ST2 R 0 0 0 0 0 0 0 0 F3H USI1 Baud Rate Generation Register USI1BD R W 1 1 1 1 1 1 1 1 F4H USI1 SDA Hold Time Register USI1SDHR R ...

Page 59: ...4PPRL R W 1 1 1 1 1 1 1 1 1009H Timer 4 PWM Period High Register T4PPRH R W 0 0 100AH Timer 4 PWM A Duty Low Register T4ADRL R W 0 1 1 1 1 1 1 1 100BH Timer 4 PWM A Duty High Register T4ADRH R W 0 0 100CH Timer 4 PWM B Duty Low Register T4BDRL R W 0 1 1 1 1 1 1 1 100DH Timer 4 PWM B Duty High Register T4BDRH R W 0 0 100EH Timer 4 PWM C Duty Low Register T4CDRL R W 0 1 1 1 1 1 1 1 100FH Timer 4 PWM...

Page 60: ...R W R W R W R W R W R W Initial value 00H B B Register SP Stack Pointer 81H 7 6 5 4 3 2 1 0 SP R W R W R W R W R W R W R W R W Initial value 07H SP Stack Pointer DPL Data Pointer Register Low 82H 7 6 5 4 3 2 1 0 DPL R W R W R W R W R W R W R W R W Initial value 00H DPL Data Pointer Low DPH Data Pointer Register High 83H 7 6 5 4 3 2 1 0 DPH R W R W R W R W R W R W R W R W Initial value 00H DPH Data...

Page 61: ... 00H CY Carry Flag AC Auxiliary Carry Flag F0 General Purpose User Definable Flag RS1 Register Bank Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User Definable Flag P Parity Flag Set Cleared by hardware each instruction cycle to indicate an odd even number of 1 bits in the accumulator EO Extended Operation Register A2H 7 6 5 4 3 2 1 0 TRAP_EN DPSEL2 DPSEL1 DPSEL0 R W R W R W R W...

Page 62: ...as an input mode Set bits of this register will make the pin to output mode Almost bits are cleared by a system reset but some bits are set by a system reset 9 2 3 Pull up Resistor Selection Register PxPU The on chip pull up resistor can be connected to I O ports individually with a pull up resistor selection register PxPU The pull up register selection controls the pull up resister enable disable...

Page 63: ...lection Register P15DB DFH R W 00H P1 P5 Debounce Enable Register P1FSRH D5H R W 00H P1 Function Selection High Register P1FSRL D4H R W 00H P1 Function Selection Low Register P2 90H R W 00H P2 Data Register P2IO B9H R W 00H P2 Direction Register P2PU AEH R W 00H P2 Pull up Resistor Selection Register P2OD 93H R W 00H P2 Open drain Selection Register P2FSRH D7H R W 00H P2 Function Selection High Re...

Page 64: ... P0 Data Register 80H 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 R W R W R W R W R W R W R W R W Initial value 00H P0 7 0 I O Data P0IO P0 Direction Register A1H 7 6 5 4 3 2 1 0 P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO R W R W R W R W R W R W R W R W Initial value 00H P0IO 7 0 P0 Data I O Direction 0 Input 1 Output NOTE 1 EC3 EINT0 EINT5 function possible when input P0PU P0 Pull up Res...

Page 65: ... 4 1 0 fx 4096 1 1 Reserved P07DB Configure De bounce of P07 Port 0 Disable 1 Enable P06DB Configure De bounce of P06 Port 0 Disable 1 Enable P05DB Configure De bounce of P05 Port 0 Disable 1 Enable P04DB Configure De bounce of P04 Port 0 Disable 1 Enable P03DB Configure De bounce of P03 Port 0 Disable 1 Enable P02DB Configure De bounce of P02 Port 0 Disable 1 Enable NOTE 1 If the same level is no...

Page 66: ...4 Description 0 0 I O Port EINT5 function possible when input 0 1 SEG22 Function 1 0 AN5 Function 1 1 PWM4CB Function P0FSRH 3 2 P06 Function Select P0FSRH3 P0FSRH2 Description 0 0 I O Port EINT4 function possible when input 0 1 SEG23 Function 1 0 AN4 Function 1 1 PWM4CA Function P0FSRH 1 0 P05 Function Select P0FSRH1 P0FSRH0 Description 0 0 I O Port EINT3 function possible when input 0 1 SEG24 Fu...

Page 67: ...ort EINT2 function possible when input 0 1 SEG25 Function 1 0 AN2 Function 1 1 PWM4BA Function P0FSRL 4 3 P03 Function Select P0FSRL4 P0FSRL3 Description 0 0 I O Port EINT1 function possible when input 0 1 SEG26 Function 1 0 AN1 Function 1 1 PWM4AB Function P0FSRL 2 1 P02 Function Select P0FSRL2 P0FSRL1 Description 0 0 I O Port EINT0 function possible when input 0 1 AVREF Function 1 0 AN0 Function...

Page 68: ...Register 88H 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 R W R W R W R W R W R W R W R W Initial value 00H P1 7 0 I O Data P1IO P1 Direction Register B1H 7 6 5 4 3 2 1 0 P17IO P16IO P15IO P14IO P13IO P12IO P11IO P10IO R W R W R W R W R W R W R W R W Initial value 00H P1IO 7 0 P1 Data I O Direction 0 Input 1 Output NOTE 1 EINT6 ENINT7 EINT11 EINT12 SS2 EC1 function possible when input P1PU P1 P...

Page 69: ...P52 Port 0 Disable 1 Enable P17DB Configure De bounce of P17 Port 0 Disable 1 Enable P16DB Configure De bounce of P16 Port 0 Disable 1 Enable P12DB Configure De bounce of P12 Port 0 Disable 1 Enable P11DB Configure De bounce of P11 Port 0 Disable 1 Enable NOTE 1 If the same level is not detected on enabled pin three or four times in a row at the sampling clock the signal is eliminated as noise 2 A...

Page 70: ...6 SS2 function possible when input 0 1 SEG21 Function 1 0 AN6 Function 1 1 Not used P1FSRH 5 4 P16 Function Select P1FSRH5 P1FSRH4 Description 0 0 I O Port EINT7 function possible when input 0 1 SEG20 Function 1 0 AN7 Function 1 1 SCK2 Function P1FSRH 3 2 P15 Function Select P1FSRH3 P1FSRH2 Description 0 0 I O Port 0 1 SEG19 Function 1 0 AN8 Function 1 1 MISO2 Function P1FSRH 1 0 P14 Function Sele...

Page 71: ... 1 SEG17 Function 1 0 AN10 Function 1 1 BUZO Function P1FSRL 5 4 P12 Function Select P1FSRL5 P1FSRL4 Description 0 0 I O Port EINT11 function possible when input 0 1 SEG16 Function 1 0 AN11 Function 1 1 T1O PWM1O Function P1FSRL 3 2 P11 Function Select P1FSRL3 P1FSRL2 Description 0 0 I O Port EINT12 function possible when input 0 1 SEG15 Function 1 0 AN12 Function 1 1 T2O PWM2O Function P1FSRL 1 0...

Page 72: ... the port function selection registers for the P2 function selection 9 5 2 Register description for P2 P2 P2 Data Register 90H 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 R W R W R W R W R W R W R W R W Initial value 00H P2 7 0 I O Data P2IO P2 Direction Register B9H 7 6 5 4 3 2 1 0 P27IO P26IO P25IO P24IO P23IO P22IO P21IO P20IO R W R W R W R W R W R W R W R W Initial value 00H P2IO 7 0 P2 Da...

Page 73: ... R W R W R W R W R W R W R W R W Initial value 00H P2PU 7 0 Configure Pull up Resistor of P2 Port 0 Disable 1 Enable P2OD P2 Open drain Selection Register 93H 7 6 5 4 3 2 1 0 P27OD P26OD P25OD P24OD P23OD P22OD P21OD P20OD R W R W R W R W R W R W R W R W Initial value 00H P2OD 7 0 Configure Open drain of P2 Port 0 Push pull output 1 Open drain output ...

Page 74: ... SEG9 Function P2FSRL Port 2 Function Selection Low Register D6H 7 6 5 4 3 2 1 0 P2FSRL5 P2FSRL4 P2FSRL3 P2FSRL2 P2FSRL1 P2FSRL0 R W R W R W R W R W R W Initial value 00H P2FSRL5 P23 Function Select 0 I O Port 1 SEG10 Function P2FSRL4 P22 Function Select 0 I O Port SS1 function possible when input 1 SEG11 Function P2FSRL 3 2 P21 Function Select P2FSRL3 P2FSRL2 Description 0 0 I O Port 0 1 SEG12 Fu...

Page 75: ... Register 98H 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 R W R W R W R W R W R W R W R W Initial value 00H P3 7 0 I O Data P3IO P3 Direction Register C1H 7 6 5 4 3 2 1 0 P37IO P36IO P35IO P34IO P33IO P32IO P31IO P30IO R W R W R W R W R W R W R W R W Initial value 00H P3IO 7 0 P3 Data I O Direction 0 Input 1 Output P3PU P3 Pull up Resistor Selection Register AFH 7 6 5 4 3 2 1 0 P37PU P36PU P35...

Page 76: ...O Port 1 COM3 SEG1 Function P3FSR3 P33 Function select 0 I O Port 1 COM4 SEG2 or COM0 Function P3FSR2 P32 Function Select 0 I O Port 1 COM5 SEG3 or COM1 Function P3FSR1 P31 Function select 0 I O Port 1 COM6 SEG4 or COM2 SEG4 Function P3FSR0 P30 Function Select 0 I O Port 1 COM7 SEG5 or COM3 SEG5 Function NOTE 1 The P30 P35 is automatically configured as common or segment signal according to the du...

Page 77: ... selection 9 7 2 Register description for P4 P4 P4 Data Register A0H 7 6 5 4 3 2 1 0 P43 P42 P41 P40 R W R W R W R W Initial value 00H P4 3 0 I O Data P4IO P4 Direction Register C9H 7 6 5 4 3 2 1 0 P43IO P42IO P41IO P40IO R W R W R W R W Initial value 00H P4IO 3 0 P4 Data I O Direction 0 Input 1 Output NOTE 1 SS0 function possible when input P4PU P4 Pull up Resistor Selection Register A3H 7 6 5 4 ...

Page 78: ...FSR2 P4FSR1 P4FSR0 R W R W R W R W R W R W R W Initial value 00H P4FSR6 P43 Function Select 0 I O Port SS0 function possible when input 1 VLC0 Function P4FSR 5 4 P42 Function Select P4FSR5 P4FSR4 Description 0 0 I O Port 0 1 VLC1 Function 1 0 SCK0 Function 1 1 Not used P4FSR 3 2 P41 Function Select P4FSR3 P4FSR2 Description 0 0 I O Port 0 1 VLC2 Function 1 0 TXD0 SDA0 MOSI0 Function 1 1 Not used P...

Page 79: ...Register B0H 7 6 5 4 3 2 1 0 P55 P54 P53 P52 P51 P50 R W R W R W R W R W R W Initial value 00H P5 5 0 I O Data P5IO P5 Direction Register D1H 7 6 5 4 3 2 1 0 P55IO P54IO P53IO P52IO P51IO P50IO R W R W R W R W R W R W Initial value 00H P5IO 5 0 P5 Data I O Direction 0 Input 1 Output NOTE 1 EC0 EINT8 EINT10 BLNK function possible when input P5PU P5 Pull up Resistor Selection Register 95H 7 6 5 4 3 ...

Page 80: ...ct 0 I O Port EINT10 function possible when input 1 SXOUT Function P5FSR 4 3 P53 Function Select P5FSR4 P5FSR3 Description 0 0 I O Port 0 1 SXIN Function 1 0 T0O PWM0O Function 1 1 Not used P5FSR2 P51 Function Select 0 I O Port 1 XIN Function P5FSR 1 0 P50 Function Select P5FSR1 P5FSR0 Description 0 0 I O Port 0 1 XOUT Function 1 0 Not used 1 1 Not used NOTE 1 Refer to the configure option for the...

Page 81: ...ts of IE IE1 IE2 IE3 register individually enable disable a particular interrupt source Overall interrupts are controlled by EA bit 7 of IE When EA is set to 0 all interrupts are disabled when EA is set to 1 interrupts are individually enabled or disabled through the other bits of the interrupt enable registers The EA bit is always cleared to 0 jumping to an interrupt service vector and set to 1 e...

Page 82: ...Interrupt 18 Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20 Interrupt 3 Interrupt 9 Interrupt 15 Interrupt 21 Interrupt 4 Interrupt 10 Interrupt 16 Interrupt 22 Interrupt 5 Interrupt 11 Interrupt 17 Interrupt 23 Highest Lowest Highest Lowest Table 10 1 Interrupt Group Priority Level ...

Page 83: ...rupt source has enable disable bits The External interrupt flag 0 register EIFLAG0 and external interrupt flag 1 register 1 EIFLAG1 provides the status of external interrupts EINT1 Pin EINT3 Pin EINT5 Pin EINT7 Pin EINT0 Pin FLAG0 FLAG1 EINT2 Pin FLAG2 FLAG3 EINT4 Pin FLAG4 FLAG5 EINT6 Pin FLAG6 FLAG7 EINT11 Pin FLAG11 EINT12 Pin FLAG12 EIPOL1 2 2 EIPOL0H EIPOL0L 2 2 2 2 2 2 INT1 Interrupt INT11 I...

Page 84: ...LAG0 6 EIFLAG0 7 Timer 0 overflow Timer 0 Timer 1 Timer 2 Timer 3 IP1 IP IE FLAG10 FLAG11 IE2 T0OVIFR T0IFR T1IFR T2IFR T3IFR FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 EIPOL1 USI0 I2C USI0 Rx USI0 Tx IE1 I2C0IFR ADC WT WDT BIT ADCIFR WTIFR WDTIFR BITIFR Level 0 Level 1 Level 2 Level 3 EIPOL0H L USI1 I2C USI1 Rx USI1 Tx I2C1IFR SPI2 SPIIFR EINT12 EIFLAG1 3 FLAG12 EIPOL1 IE3 EINT8 EIFLAG1 0 FL...

Page 85: ...I0 Rx Interrupt INT9 IE1 3 10 Maskable 004BH USI0 Tx Interrupt INT10 IE1 4 11 Maskable 0053H External Interrupt 12 INT11 IE1 5 12 Maskable 005BH T0 Overflow Interrupt INT12 IE2 0 13 Maskable 0063H T0 Match Interrupt INT13 IE2 1 14 Maskable 006BH T1 Match Interrupt INT14 IE2 2 15 Maskable 0073H T2 Match Interrupt INT15 IE2 3 16 Maskable 007BH T3 Match Interrupt INT16 IE2 4 17 Maskable 0083H T4 Inte...

Page 86: ...rrent instruction it needs 3 9 machine cycles to go to the interrupt service routine The interrupt service task is terminated by the interrupt return instruction RETI The following process is the flow of whole interrupt service routine Figure 10 3 Interrupt Sequence Flow Saves PC value in order to continue process again after executing ISR IE EA Flag 0 1 Program Counter low Byte SP SP 1 M SP PCL 2...

Page 87: ...ng of Interrupt Enable Register Case b Interrupt flag Register Figure 10 5 Effective Timing of Interrupt Flag Register Interrupt Enable Register command Next Instruction Next Instruction After executing IE set clear enable register is effective Interrupt Flag Register Command Next Instruction Next Instruction After executing next instruction interrupt flag result is effective ...

Page 88: ... INT1 is occurred Then INT0 is served immediately and then the remain part of INT1 service routine is executed If the priority level of INT0 is same or lower than INT1 INT0 will be served after the INT1 service has completed An interrupt service routine may be only interrupted by an interrupt of higher priority and if two interrupts of different priority occur at the same time the higher level int...

Page 89: ... Saving Restore Process Diagram and Sample Source Interrupt Latched Interrupt goes Active System Clock Max 4 Machine Cycle 4 Machine Cycle Interrupt Processing LCALL LJMP Interrupt Routine 02H 25H 00B3H 00B4H Basic Interval Timer Vector Table Address 0EH 2EH 0125H 0126H Basic Interval Timer Service Routine Address 01H 00B5H Main Task Saving Register Restoring Register Interrupt Service Task INTxx ...

Page 90: ... 12 1 Interrupt Enable Register IE IE1 IE2 IE3 Interrupt enable register consists of global interrupt control bit EA and peripheral interrupt control bits Total 24 peripherals are able to control interrupt 10 12 2 Interrupt Priority Register IP IP1 The 24 interrupts are divided into 6 groups which have each 4 interrupt sources A group can be assigned 4 levels interrupt priority using interrupt pri...

Page 91: ... 00H Interrupt Enable Register 2 IE3 ABH R W 00H Interrupt Enable Register 3 IP B8H R W 00H Interrupt PriorityRegister IP1 F8H R W 00H Interrupt PriorityRegister 1 EIFLAG0 C0H R W 00H External Interrupt Flag 0 Register EIPOL0L A4H R W 00H External Interrupt Polarity 0 Low Register EIPOL0H A5H R W 00H External Interrupt Polarity 0 High Register EIFLAG1 A6H R W 00H External Interrupt Flag 1 Register...

Page 92: ...ts 0 All Interrupt disable 1 All Interrupt enable INT5E Enable or Disable External Interrupt 0 7 EINT0 EINT7 0 Disable 1 Enable INT4E Enable or Disable USI1 Tx Interrupt 0 Disable 1 Enable INT3E Enable or Disable USI1 Rx Interrupt 0 Disable 1 Enable INT2E Enable or Disable USI1 I2C Interrupt 0 Disable 1 Enable INT1E Enable or Disable External Interrupt 11 EINT11 0 Disable 1 Enable INT0E Enable or ...

Page 93: ...Initial value 00H INT11E Enable or Disable External Interrupt 12 EINT12 0 Disable 1 Enable INT10E Enable or Disable USI0 Tx Interrupt 0 Disable 1 Enable INT9E Enable or Disable USI0 Rx Interrupt 0 Disable 1 Enable INT8E Enable or Disable USI0 I2C Interrupt 0 Disable 1 Enable INT6E Enable or Disable External Interrupt 8 EINT8 0 Disable 1 Enable ...

Page 94: ... Timer 1 Match Interrupt 0 Disable 1 Enable INT13E Enable or Disable Timer 0 I Match Interrupt 0 Disable 1 Enable INT12E Enable or Disable Timer 0 Overflow Interrupt 0 Disable 1 Enable IE3 Interrupt Enable Register 3 ABH 7 6 5 4 3 2 1 0 INT22E INT21E INT20E INT19E INT18E R W R W R W R W R W Initial value 00H INT22E Enable or Disable BIT Interrupt 0 Disable 1 Enable INT21E Enable or Disable WDT Int...

Page 95: ... IP1 IP0 R W R W R W R W R W R W Initial value 00H IP1 Interrupt Priority Register 1 F8H 7 6 5 4 3 2 1 0 IP15 IP14 IP13 IP12 IP11 IP10 R W R W R W R W R W R W Initial value 00H IP 5 0 IP1 5 0 Select Interrupt Group Priority IP1x IPx Description 0 0 level 0 lowest 0 1 level 1 1 0 level 2 1 1 level 3 highest ...

Page 96: ...L7 POL6 POL5 POL4 R W R W R W R W R W R W R W R W Initial value 00H EIPOL0H 7 0 External interrupt EINT7 EINT6 EINT5 EINT4 polarity selection POLn 1 0 Description 0 0 No interrupt at any edge 0 1 Interrupt on rising edge 1 0 Interrupt on falling edge 1 1 Interrupt on both of rising and falling edge Where n 4 5 6 and 7 EIPOL0L External Interrupt Polarity 0 Low Register A4H 7 6 5 4 3 2 1 0 POL3 POL2...

Page 97: ... interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or automatically clear by INT_ACK signal Writing 1 has no effect 0 T3 Interrupt no generation 1 T3 Interrupt generation EIFLAG1 3 0 When an External Interrupt EINT8 EINT10 EINT12 is occurred the flag becomes 1 The flag is cleared by writing 0 to the bit or automatically cleared by INT_ACK signal Writing 1 has no effect 0 Ext...

Page 98: ...tively The main sub clock can be also obtained from the external oscillator In this case it is necessary to put the external clock signal into the XIN SXIN pin and open the XOUT SXOUT pin The default system clock is 1MHz INT RC Oscillator and the default division rate is eight In order to stabilize system internally it is used 1MHz INT RC oscillator on POR Calibrated Internal RC Oscillator 16MHz I...

Page 99: ...Main OSC fXIN STOP Mode XCLKE Internal RC OSC 16MHz STOP Mode IRCE fIRC 1 1 1 2 1 4 1 8 M U X WDTRC OSC 5kHz WDTCK Stabilization Time Generation M U X BIT clock WDT clock SXIN SXOUT Sub OSC fSUB STOP Mode SCLKE WT 2 SCLK 1 0 256 1 16 1 32 3 IRCS 2 0 fx 4096 fx 1024 fx 128 fx 16 M U X 2 BITCK 1 0 SCLK fx Figure 11 1 Clock Generator Block Diagram ...

Page 100: ...er Description The clock generator register uses clock control for system operation The clock generation consists of System and clock control register and oscillator control register 11 1 5 Register Description for Clock Generator SCCR System and Clock Control Register 8AH 7 6 5 4 3 2 1 0 SCLK1 SCLK0 R W R W Initial value 00H SCLK 1 0 System Clock Selection Bit SCLK1 SCLK0 Description 0 0 INT RC O...

Page 101: ...Hz 0 1 1 INT RC 4 4MHz 1 0 0 INT RC 2 8MHz 1 0 1 INT RC 1 16MHz Other values Not used IRCE Control the Operation of the Internal RC Oscillator 0 Enable operation of INT RC OSC 1 Disable operation of INT RC OSC XCLKE Control the Operation of the External Main Oscillator 0 Disable operation of X TAL 1 Enable operation of X TAL SCLKE Control the Operation of the External Sub Oscillator 0 Disable oper...

Page 102: ...ically cleared to 00000b immediately after XTFLSR write 0x00 on read 10101b Write 0x15 to these bits with valid XRNS 2 0 Other values Write is ignored XRNS External Main Oscillator Range selection This bit is effective only when the fXIN is selected for system clock XRNS Description 0 4 2MHz x tal 8 5MHz 1 x tal 4 2MHz NOTE 1 The External Main Oscillator Range XRNS should be changed while the syst...

Page 103: ... features During Power On BIT gives a stable clock generation time On exiting Stop mode BIT gives a stable clock generation time As timer function timer interrupt occurrence 11 2 2 Block Diagram BIT Clock BCK 2 0 8 Bit Up Counter BITCNT BCLR clear BITIFR To interrupt block selected bit overflow WDT INT_ACK clear Start CPU RESET STOP Figure 11 2 Basic Interval Timer Block Diagram 11 2 3 Register Ma...

Page 104: ...6 5 4 3 2 1 0 BITIFR BITCK1 BITCK0 BCLR BCK2 BCK1 BCK0 R W R W R W R W R W R W R W Initial value 01H BITIFR When BIT Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 BIT interrupt no generation 1 BIT interrupt generation BITCK 1 0 Select BIT clock source BITCK1 BITCK0 Description 0 0 fx 4096 0 1 fx 1024 1 0 fx 128 1 ...

Page 105: ...ts up After 1 machine cycle this bit is cleared to 0 automatically The watchdog timer consists of 8 bit binary counter and the watchdog timer data register When the value of 8 bit binary counter is equal to the 8 bits of WDTCNT the interrupt request flag is generated This can be used as Watchdog timer interrupt or reset of CPU in accordance with the bit WDTRSON The input clock source of watch dog ...

Page 106: ...p Name Address Direction Default Description WDTCNT 8EH R 00H Watch Dog Timer Counter Register WDTDR 8EH W FFH Watch Dog Timer Data Register WDTCR 8DH R W 00H Watch Dog Timer Control Register Table 11 3 Watch Dog Timer Register Map 11 3 5 Watch Dog Timer Register Description The watch dog timer register consists of watch dog timer counter register WDTCNT watch dog timer data register WDTDR and wat...

Page 107: ...Value 1 NOTE 1 Do not write 0 in the WDTDR register WDTCR Watch Dog Timer Control Register 8DH 7 6 5 4 3 2 1 0 WDTEN WDTRSON WDTCL WDTCK WDTIFR R W R W R W R W R W Initial value 00H WDTEN Control WDT Operation 0 Disable 1 Enable WDTRSON Control WDT RESET Operation 0 Free Running 8 bit timer 1 Watch Dog Timer RESET ON WDTCL Clear WDT Counter 0 Free Run 1 Clear WDT Counter auto clear after 1 Cycle W...

Page 108: ...rcuits is composed of 21 bit counter Low 14 bit is binary counter and high 7 bit is auto reload counter in order to raise resolution In WTR it can control WT clear and set Interval value at write time and it can read 7 bit WT counter value at read time The watch timer supplies the clock frequency for the LCD driver fLCD Therefore if the watch timer is disabled the LCD driver controller does not op...

Page 109: ... WTCR can control the clock source WTCK 1 0 interrupt interval WTIN 1 0 and function enable disable WTEN Also there is WT interrupt flag bit WTIFR 11 4 5 Register Description for Watch Timer WTCNT Watch Timer Counter Register Read Case 89H 7 6 5 4 3 2 1 0 WTCNT6 WTCNT5 WTCNT4 WTCNT3 WTCNT2 WTCNT1 WTCNT0 R R R R R R R Initial value 00H WTCNT 6 0 WT Counter WTDR Watch Timer Data Register Write Case ...

Page 110: ...r by INT_ACK signal Writing 1 has no effect 0 WT Interrupt no generation 1 WT Interrupt generation WTIN 1 0 Determine interrupt interval WTIN1 WTIN0 Description 0 0 fWCK 2 7 0 1 fWCK 2 13 1 0 fWCK 2 14 1 1 fWCK 2 14 x 7bit WTDR Value 1 WTCK 1 0 Determine Source Clock WTCK1 WTCK0 Description 0 0 fSUB 0 1 fX 256 1 0 fX 128 1 1 fX 64 NOTE 1 fX System clock frequency Where fx 4 19MHz 2 fSUB Sub clock ...

Page 111: ... or an external clock source EC0 The clock source is selected by clock selection logic which is controlled by the clock selection bits T0CK 2 0 TIMER0 clock source fX 2 4 8 32 128 512 2048 EC0 In the capture mode by EINT10 the data is captured into input capture data register T0CDR In timer counter mode whenever counter value is equal to T0DR T0O port toggles Also the timer 0 outputs PWM waveform ...

Page 112: ...ternal clock EC0 counts up the timer at the rising edge If the EC0 is selected as a clock source by T0CK 2 0 EC0 port should be set to the input port by P52IO bit P r e s c a l e r fx M U X fx 2 T0CNT 8Bit EC0 fx 4 fx 8 fx 32 fx 128 fx 512 fx 2048 3 T0CK 2 0 T0EN 8 bit Timer 0 Counter T0DR 8Bit Comparator T0IFR T0O PWM0O 8 bit Timer 0 Data Register INT_ACK Clear Match signal Clear Match MUX T0MS 1...

Page 113: ...er 0 occurs In PWM mode the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H The timer 0 overflow interrupt is generated whenever a counter overflow occurs T0CNT value is cleared by software T0CC bit P r e s c a l e r fx M U X fx 2 T0CNT 8Bit EC0 fx 4 fx 8 fx 32 fx 128 fx 512 fx 2048 3 T0CK 2 0 T0EN 8 bit Timer 0 Count...

Page 114: ...M 00H 01H 02H 4AH FFH FEH 00H T0 Match Interrupt T0 Overflow Interrupt T0DR 1 T0DR 4AH Timer 0 clock Set T0EN T0PWM T0 Match Interrupt 2 T0DR 00H T0PWM T0 Match Interrupt 3 T0DR FFH PWM Mode T0MS 01b Figure 11 9 PWM Output Waveforms in PWM Mode for Timer 0 ...

Page 115: ... output T0O waveform is not available According to EIPOL1 registers setting the external interrupt EINT10 function is chosen Of course the EINT10 pin must be set to an input port T0CDR and T0DR are in the same address In the capture mode reading operation reads T0CDR not T0DR and writing operation will update T0DR P r e s c a l e r fx M U X fx 2 T0CNT 8Bit EC0 fx 4 fx 8 fx 32 fx 128 fx 512 fx 2048...

Page 116: ...rflow in Capture Mode T0CNT Value Interrupt Request FLAG10 TIME 1 2 3 4 5 6 n 2 n 1 n Interrupt Interval Period 0 Count Pulse Period PCP Up count T0CDR Load Ext EINT10 PIN T0CNT Interrupt Request FLAG10 XXH Interrupt Interval Period FFH 01H FFH 01H YYH 01H Ext EINT10 PIN Interrupt Request T0IFR FFH FFH YYH 00H 00H 00H 00H 00H ...

Page 117: ...MS 1 0 2 T0MS 1 0 2 Match signal T0CC Figure 11 13 8 bit Timer 0 Block Diagram 11 5 6 Register Map Name Address Direction Default Description T0CNT B3H R 00H Timer 0 Counter Register T0DR B4H R W FFH Timer 0 Data Register T0CDR B4H R 00H Timer 0 Capture Data Register T0CR B2H R W 00H Timer 0 Control Register Table 11 6 Timer 0 Register Map 11 5 7 Timer Counter 0 Register Description The timer coun...

Page 118: ... R R R Initial value 00H T0CNT 7 0 T0 Counter T0DR Timer 0 Data Register B4H 7 6 5 4 3 2 1 0 T0DR7 T0DR6 T0DR5 T0DR4 T0DR3 T0DR2 T0DR1 T0DR0 R W R W R W R W R W R W R W R W Initial value FFH T0DR 7 0 T0 Data T0CDR Timer 0 Capture Data Register Read Case Capture mode only B4H 7 6 5 4 3 2 1 0 T0CDR7 T0CDR6 T0CDR5 T0CDR4 T0CDR3 T0CDR2 T0CDR1 T0CDR0 R R R R R R R R Initial value 00H T0CDR 7 0 T0 Captu...

Page 119: ...ter mode 0 1 PWM mode 1 x Capture mode T0CK 2 0 Select Timer 0 clock source fx is a system clock frequency T0CK2 T0CK1 T0CK0 Description 0 0 0 fx 2 0 0 1 fx 4 0 1 0 fx 8 0 1 1 fx 32 1 0 0 fx 128 1 0 1 fx 512 1 1 0 fx 2048 1 1 1 External Clock EC0 T0CC Clear timer 0 Counter 0 No effect 1 Clear the Timer 0 counter When write automatically cleared 0 after being cleared counter NOTE 1 Match Interrupt ...

Page 120: ...1 outputs PWM wave form through PWM1O port in the PPG mode T1EN P1FSRL 5 4 T1MS 1 0 T1CK 2 0 Timer 1 1 11 00 XXX 16 bit Timer Counter Mode 1 00 01 XXX 16 bit Capture Mode 1 11 10 XXX 16 bit PPG Mode one shot mode 1 11 11 XXX 16 bit PPG Mode repeat mode Table 11 7 Timer 1 Operating Modes 11 6 2 16 bit Timer Counter Mode The 16 bit timer counter mode is selected by control register as shown in Figur...

Page 121: ...o interrupt block A Match Buffer Register A A Match T1CC Reload Pulse Generator T1O R T1EN 3 T1CK 2 0 2 T1MS1 T1MS0 T1CC 0 0 X T1CK2 T1CRL X ADDRESS BAH INITIAL VALUE 0000_0000B T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR X X X X X X T1EN Figure 11 14 16 bit Timer Counter Mode for Timer 1 Figure 11 15 16 bit Timer Counter 1 Example T1CNTH L Value Timer 1 T1IFR Interrupt TIME 1 2 3 4 5 6 n 2 n 1 n Interru...

Page 122: ...T1BDRH T1BDRL According to EIPOL1 registers setting the external interrupt EINT11 function is chosen Of course the EINT11 pin must be set as an input port A Match T1CC T1EN P r e s c a l e r fx M U X fx 2 fx 4 fx 64 fx 512 fx 2048 fx 8 fx 1 16 bit Counter T1CNTH T1CNTL 16 bit B Data Register T1BDRH T1BDRL Clear Edge Detector T1ECE EC1 Comparator 16 bit A Data Register T1ADRH T1ADRL T1IFR INT_ACK C...

Page 123: ...Capture Mode T1CNTH L Value Interrupt Request FLAG11 TIME 1 2 3 4 5 6 n 2 n 1 n Interrupt Interval Period 0 Count Pulse Period PCP Up count T1BDRH L Load Ext EINT11 PIN T1CNTH L Interrupt Request FLAG11 XXH Interrupt Interval Period FFFFH 01H FFFFH 01H YYH 01H Ext EINT11 PIN Interrupt Request T1IFR FFFFH FFFFH YYH 00H 00H 00H 00H 00H ...

Page 124: ...64 fx 512 fx 2048 fx 8 fx 1 Comparator 16 bit Counter T1CNTH T1CNTL 16 bit B Data Register T1BDRH T1BDRL Clear B Match Edge Detector T1ECE EC1 Buffer Register B Comparator 16 bit A Data Register T1ADRH T1ADRL T1IFR INT_ACK Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T1O PWM1O R T1EN 3 T1CK 2 0 2 T1EN T1CRH 1 ADDRESS BBH INITIAL VALUE 0000_0000B T1MS1 T1MS0 T1CC 1 1 X ...

Page 125: ...1 T1BDRH L 5 T1ADRH L PWM1O A Match 2 T1BDRH L T1ADRH L PWM1O A Match 3 T1BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 1 clock Counter T1ADRH L T1 Interrupt PWM1O B Match One shot Mode T1MS 10b and Start High T1POL 0b Set T1EN 0 Clear and Start 3 7 M A Match 1 T1BDRH L 5 T1ADRH L PWM1O A Match 2 T1BDRH L T1ADRH L PWM1O A Match 3 T1BDRH L 0000H Low Level Figure 11 20 16 bit PPG Mode Timming cha...

Page 126: ... PWM1O R EINT11 T1CNTR T1EN 3 T1CK 2 0 Clear EIPOL1 5 4 FLAG11 EIFLAG1 2 INT_ACK Clear To interrupt block 2 2 T1MS 1 0 2 Edge Detector T1ECE EC1 To Timer 2 block A Match T1CC T1EN A Match T1CC T1EN Figure 11 21 16 bit Timer 1 Block Diagram 11 6 6 Register Map Name Address Direction Default Description T1ADRH BDH R W FFH Timer 1 A Data High Register T1ADRL BCH R W FFH Timer 1 A Data Low Register T1...

Page 127: ...W R W R W R W Initial value FFH T1ADRH 7 0 T1 A Data High Byte T1ADRL Timer 1 A Data Low Register BCH 7 6 5 4 3 2 1 0 T1ADRL7 T1ADRL6 T1ADRL5 T1ADRL4 T1ADRL3 T1ADRL2 T1ADRL1 T1ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T1ADRL 7 0 T1 A Data Low Byte NOTE 1 Do not write 0000H in the T1ADRH T1ADRL register when PPG mode T1BDRH Timer 1 B Data High Register BFH 7 6 5 4 3 2 1 0 T1BDRH7 T1BD...

Page 128: ...sable 1 Timer 1 enable Counter clear and start T1MS 1 0 Control Timer 1 Operation Mode T1MS1 T1MS0 Description 0 0 Timer counter mode T1O toggle at A match 0 1 Capture mode The A match interrupt can occur 1 0 PPG one shot mode PWM1O 1 1 PPG repeat mode PWM1O T1CC Clear Timer 1 Counter 0 No effect 1 Clear the Timer 1 counter When write automatically cleared 0 after being cleared counter ...

Page 129: ...ock EC1 T1IFR When T1 Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 T1 Interrupt no generation 1 T1 Interrupt generation T1POL T1O PWM1O Polarity Selection 0 Start High T1O PWM1O is low level at disable 1 Start Low T1O PWM1O is high level at disable T1ECE Timer 1 External Clock Edge Selection 0 External clock fall...

Page 130: ...er output and T1 A Match timer 1 A match signal The clock source is selected by clock selection logic which is controlled by the clock selection bits T2CK 2 0 TIMER 2 clock source fX 1 2 4 8 32 128 512 T1 A Match In the capture mode by EINT12 the data is captured into input capture data register T2BDRH T2BDRL In timer counter mode whenever counter value is equal to T2ADRH L T2O port toggles Also t...

Page 131: ...2 occurs The T2CNTH T2CNTL values are automatically cleared by match signal It can be also cleared by software T2CC T2MS 1 0 T2POL A Match T2CC T2EN P r e s c a l e r fx M U X fx 2 fx 4 fx 32 fx 128 fx 512 fx 8 fx 1 16 bit Counter T2CNTH T2CNTL Clear T1 A Match Comparator 16 bit A Data Register T2ADRH T2ADRL T2IFR INT_ACK Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T2...

Page 132: ...d Figure 11 23 16 bit Timer Counter 2 Example T2CNTH L Value Timer 2 T2IFR Interrupt TIME 1 2 3 4 5 6 n 2 n 1 n Interrupt Period PCP x n 1 0 Count Pulse Period PCP Up count Match with T2ADRH L Occur Interrupt Occur Interrupt Occur Interrupt ...

Page 133: ... not available According to EIPOL1 registers setting the external interrupt EINT12 function is chosen Of course the EINT12 pin must be set to an input port A Match T2CC T2EN P r e s c a l e r fx M U X fx 2 fx 4 fx 32 fx 128 fx 512 fx 8 fx 1 16 bit Counter T2CNTH T2CNTL 16 bit B Data Register T2BDRH T2BDRL Clear T1 A Match Comparator 16 bit A Data Register T2ADRH T2ADRL T2IFR INT_ACK Clear To inter...

Page 134: ...Capture Mode T2CNTH L Interrupt Request FLAG12 XXH Interrupt Interval Period FFFFH 01H FFFFH 01H YYH 01H Ext EINT12 PIN Interrupt Request T2IFR FFFFH FFFFH YYH 00H 00H 00H 00H 00H T2CNTH L Value Interrupt Request FLAG12 TIME 1 2 3 4 5 6 n 2 n 1 n Interrupt Interval Period 0 Count Pulse Period PCP Up count T2BDRH L Load Ext EINT12 PIN ...

Page 135: ...1 Comparator 16 bit Counter T2CNTH T2CNTL 16 bit B Data Register T2BDRH T2BDRL Clear B Match T1 A Match Buffer Register B Comparator 16 bit A Data Register T2ADRH T2ADRL T2IFR INT_ACK Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T2O PWM2O R T2EN 3 T2CK 2 0 2 A Match T2CC T2EN A Match T2CC T2EN T2EN T2CRH 1 ADDRESS C3H INITIAL VALUE 0000_0000B T2MS1 T2MS0 T2CC 1 1 X T2C...

Page 136: ...1 T2BDRH L 5 T2ADRH L PWM2O A Match 2 T2BDRH L T2ADRH L PWM2O A Match 3 T2BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 2 clock Counter T2ADRH L T2 Interrupt PWM2O B Match One shot Mode T2MS 10b and Start High T2POL 0b Set T2EN 0 Clear and Start 3 7 M A Match 1 T2BDRH L 5 T2ADRH L PWM2O A Match 2 T2BDRH L T2ADRH L PWM2O A Match 3 T2BDRH L 0000H Low Level Figure 11 28 16 bit PPG Mode Timming cha...

Page 137: ...2EN 3 T2CK 2 0 Clear EIPOL1 7 6 FLAG12 EIFLAG1 3 INT_ACK Clear To interrupt block 2 2 T2MS 1 0 2 T1 A Match A Match T2CC T2EN A Match T2CC T2EN NOTE 1 T1 A Match is a pulse for the timer 2 clock source if it is selected Figure 11 29 16 bit Timer 2 Block Diagram 11 7 6 Register Map Name Address Direction Default Description T2ADRH C5H R W FFH Timer 2 A Data High Register T2ADRL C4H R W FFH Timer 2 ...

Page 138: ...R W R W R W R W Initial value FFH T2ADRH 7 0 T2 A Data High Byte T2ADRL Timer 2 A Data Low Register C4H 7 6 5 4 3 2 1 0 T2ADRL7 T2ADRL6 T2ADRL5 T2ADRL4 T2ADRL3 T2ADRL2 T2ADRL1 T2ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T2ADRL 7 0 T2 A Data Low Byte NOTE 1 Do not write 0000H in the T2ADRH T2ADRL register when PPG mode T2BDRH Timer 2 B Data High Register C7H 7 6 5 4 3 2 1 0 T2BDRH7 T2...

Page 139: ...sable 1 Timer 2 enable Counter clear and start T2MS 1 0 Control Timer 2 Operation Mode T2MS1 T2MS0 Description 0 0 Timer counter mode T2O toggle at A match 0 1 Capture mode The A match interrupt can occur 1 0 PPG one shot mode PWM2O 1 1 PPG repeat mode PWM2O T2CC Clear Timer 2 Counter 0 No effect 1 Clear the Timer 2 counter When write automatically cleared 0 after being cleared counter ...

Page 140: ...0 0 fx 4 1 0 1 fx 2 1 1 0 fx 1 1 1 1 T1 A Match T2IFR When T2 Match Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 T2interrupt no generation 1 T2 interrupt generation T2POL T2O PWM2O Polarity Selection 0 Start High T2O PWM2O is low level at disable 1 Start Low T2O PWM2O is high level at disable T2CNTR Timer 2 Count...

Page 141: ...e clock selection bits T3CK 2 0 T4CK 3 0 Also the timer counter 4 can use more clock sources than timer counter 3 TIMER 3 clock source fX 2 4 8 32 128 512 2048 EC3 TIMER 4 clock source fX 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 T3 clock In the capture mode by EINT0 EINT1 the data is captured into input capture data register T3CAPR T4CAPR In 8 bit timer counter 3 4 mode whenever coun...

Page 142: ...ing edge If the EC3 is selected as a clock source by T3CK 2 0 EC3 port should be set to the input port by P00IO bit Timer 4 can t use the external EC3 clock T3EN T3CR 1 ADDRESS 1000H ESFR INITIAL VALUE 0000_0000B T3MS T3CK2 T3CK1 T3CK0 T3CN T3ST 0 X X X X X 16BIT T4CR 0 ADDRESS 1002H ESFR INITIAL VALUE 0000_0000B T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0 0 X X X X X X P r e s c a l e r fx M U X fx 2 ...

Page 143: ... bit must be set to 1 Timer 3 is LSB 8 bit the timer 4 is MSB 8 bit The external clock EC3 counts up the timer at the rising edge If the EC3 is selected as a clock source by T3CK 2 0 EC3 port should be set to the input port by P00IO bit P r e s c a l e r fx M U X fx 2 T4CNT T3CNT 16Bit EC3 fx 4 fx 8 fx 32 fx 128 fx 512 fx 2048 3 T3CK 2 0 T3CN 16 bit Timer 3 Counter T4DR T3DR 16Bit Comparator T3IFR...

Page 144: ...tically cleared by match signal This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer The capture result is loaded into T3CAPR T4CAPR In the timer 3 4 capture mode timer 3 4 output T3O T4O waveform is not available According to the EIPOL0L register setting the external interrupt EINT0 and EINT1 function is chose Of cou...

Page 145: ...it Timer 4 Counter T4DR 8Bit Comparator To interrupt block T4O 8 bit Timer 4 Data Register Clear Match T4CAPR 8Bit Clear EINT1 EIPOL0L 3 2 FLAG0 EIFLAG0 1 S W Clear To interrupt block 2 T4ST 8 bit Timer 4 Capture Register P r e s c a l e r fx M U X fx 1 fx 2 fx 4 fx 8 fx 16384 T4MS T4CN T3EN T3CR 1 ADDRESS 1000H ESFR INITIAL VALUE 0000_0000B T3MS T3CK2 T3CK1 T3CK0 T3CN T3ST 1 X X X X X 16BIT T4CR ...

Page 146: ...it EC3 fx 4 fx 8 fx 32 fx 128 fx 512 fx 2048 3 T3CK 2 0 T3CN 16 bit Timer 3 Counter T4DR T3DR 16Bit Comparator T3IFR To interrupt block T3O 16 bit Timer 3 Data Register INT_ACK Clear Clear Match T4CAPR T3CAPR 16Bit Clear EINT0 EIPOL0L 1 0 FLAG0 EIFLAG0 0 S W Clear To interrupt block 2 T3MS T3ST 16 bit Timer 3 Capture Register MSB LSB MSB LSB MSB LSB T3EN T3CR 1 ADDRESS 1000H ESFR INITIAL VALUE 000...

Page 147: ...T4ADRL X Source Clock Resolution Frequency T4CK 3 0 0001 250ns T4CK 3 0 0010 500ns T4CK 3 0 0100 2us 10 bit 3 9kHz 1 95kHz 0 49kHz 9 bit 7 8kHz 3 9kHz 0 98kHz 8 bit 15 6kHz 7 8kHz 1 95kHz 7 bit 31 2kHz 15 6kHz 3 91kHz Table 11 12 PWM Frequency vs Resolution at 8MHz The POLxA bit of T4PCR3 register decides the polarity of duty cycle If the duty value is set same to the period value the PWM output i...

Page 148: ...a Register T4CDRH T4CDRL PWM Output Control C ch PWM4CA PWM Delay Control C ch PWM4CB A Match B Match C Match Interrupt Generator A Match B Match C Match Bottom Underflow To interrupt block FORCA T4PCR2 0 ADDRESS 1004H ESFR INITIAL VALUE 0000_0000B PAAOE PABOE PBAOE PBBOE PCAOE PCBOE X X X X X X HZCLR T4PCR3 X ADDRESS 1005H ESFR INITIAL VALUE 0000_0000B POLBO POLAA POLAB POLBA POLBB POLCA POLCB X ...

Page 149: ...ol C ch PWM4CA PWM Delay Control C ch PWM4CB A Match Interrupt Generator A Match B Match C Match Bottom Underflow To interrupt block FORCA T4PCR2 1 ADDRESS 1004H ESFR INITIAL VALUE 0000_0000B PAAOE PABOE PBAOE PBBOE PCAOE PCBOE X X X X X X HZCLR T4PCR3 X ADDRESS 1005H ESFR INITIAL VALUE 0000_0000B POLBO POLAA POLAB POLBA POLBB POLCA POLCB X X X X X X X 16BIT T4CR 0 ADDRESS 1002H ESFR INITIAL VALUE...

Page 150: ...ck for data transfer in the internal clock synchronization circuit So the update data is written before 3 cycle of timer clock to get the right output waveform Source Clock fx Duty Cycle 1 80H X250ns 32 25us T4CNT 00 01 02 03 04 7F 80 81 82 3FF 00 01 02 P02 PWM4AA POLAA 1 P02 PWM4AA POLAA 0 Period Cycle 1 3FFH X250ns 256us 3 9kHz T4PPRL 8 bit T4ADRL 8 bit T4PPRH 2 bit T4ADRH 2 bit 03H FFH 00H 80H ...

Page 151: ...tput Waveform Figure 11 39 Example of PWM waveform in Back to Back mode at 4 MHz T4CNT Duty Normal PWM mode Output 00H 00H 00H 00H 00H MAX MAX MAX MAX Period Duty Period Update T4CNT Duty Back to Back mode Output 00H 00H 00H MAX MAX MAX Period Duty Period Update Duty Period Non Back to Back mode Back to Back mode T4CNT P02 PWM4AA POLAA 1 T4CR 03H 2 us T4PPRH 00H T4PPRL 0BH T4ADRH 00H T4ADRL 05H So...

Page 152: ...R1 register it is possible to stop PWM operation by the software During PHLT bit being 1 PWM output becomes a reset value and internal counter becomes reset as 0 Without changing PWM setting it can temporarily stop PWM In case of T4CNT when stopping counter PWM output pin remains before states But if PHLT bit sets to 1 PWM output pin has reset value Figure 11 41 Example of PWM External Synchroniza...

Page 153: ...hat the inversion outputs of A B C channel have the same A ch output waveform According to POLAA BB CC it is able to control the inversion of outputs Figure 11 42 Example of Force Drive All Channel with A ch PWMA PAAOE PWM4AA PABOE PWM4AB PBAOE PWM4BA PBBOE PWM4BB FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE T4PCR2 1 X X X X X X ADDRESS 1004H ESFR INITIAL VALUE 0 00_0000B C ch operation is the same w...

Page 154: ...a BA BB output of the B channel duty register a CA CB output of the C channel duty register are controlled respectively If the UALL bit is set to 1 it is updated B C channel duty at the same time when it is written by a A channel duty register Figure 11 43 Example of Force Drive 6 ch Mode PWMA PAAOE PWM4AA PABOE PWM4AB PBAOE PWM4BA PBBOE PWM4BB FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE T4PCR2 0 X ...

Page 155: ...edge so the duty is reduced as the time delay In POLAA BA CA setting to 0 the delay is applied to the falling edge In POLAA BA CA setting to 1 the delay is applied to the rising edge It can produce a pair of Non overlapping clock The each channel is able to have 4 bit delay As it can select the clock up to 1 8 divided clock using NOPS 1 0 the delay of its maximum 128 timer clock cycle is produced ...

Page 156: ...DDRESS 1010H ESFR INITIAL VALUE 0000_0000B FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE T4PCR2 0 X X X X X X HZCLR POLBO POLAA POLAB POLBA POLBB POLCA T4PCR3 X X 1 1 X X X X T4DLYAA3 T4DLYAA2 T4DLYAA1 T4DLYAA0 T4DLYAB T4DLYAB T4DLYAB T4DLYAB T4DLYA 0 0 1 0 0 1 0 0 POLCB ADDRESS 1004H ESFR INITIAL VALUE 0 00_0000B ADDRESS 1005H ESFR INITIAL VALUE 0000_0000B ADDRESS 1010H ESFR INITIAL VALUE 0000_0000B ...

Page 157: ...LAG0 EIFLAG0 0 INT_ACK Clear To interrupt block 2 T3MS T3ST 8 bit Timer 3 Capture Register T4CNT 8Bit 4 T4CK 3 0 8 bit Timer 4 Counter T4DR 8Bit Comparator To interrupt block T4O 8 bit Timer 4 Data Register Clear Match T4CAPR 8Bit Clear EINT1 EIPOL0L 3 2 FLAG0 EIFLAG0 1 INT_ACK Clear To interrupt block 2 T4ST 8 bit Timer 4 Capture Register P r e s c a l e r fx M U X fx 1 fx 2 fx 4 fx 8 fx 16384 T4...

Page 158: ...fx M U X fx 2 fx 4 fx 16 fx 32 fx 64 fx 8 fx 1 Comparator 10 bit Counter 2Bit T4CNT 10 bit A Data Register T4ADRH T4ADRL Control Up Down Comparator T4PPRH T4PPRL 10Bit Period Match PWM Output Control A ch PWM4AA T4CN 4 T4CK 3 0 fx 128 fx 256 fx 1024 fx 2048 fx 4096 fx 512 fx 8192 fx 16384 Timer 4 PWM Period Register T4ST PWM Delay Control A ch PWM4AB Comparator 10 bit B Data Register T4BDRH T4BDRL...

Page 159: ...4 PWM B Duty Low Register T4CDRH 100FH ESFR R W 00H Timer 4 PWM C Duty High Register T4CDRL 100EH ESFR R W 7FH Timer 4 PWM C Duty Low Register T4DLYA 1010H ESFR R W 00H Timer 4 PWM A Delay Register T4DLYB 1011H ESFR R W 00H Timer 4 PWM B Delay Register T4DLYC 1012H ESFR R W 00H Timer 4 PWM C Delay Register T4DR 1013H ESFR R W FFH Timer 4 Data Register T4CAPR 1014H ESFR R 00H Timer 4 Capture Data R...

Page 160: ... Case Timer mode only 1001H ESFR 7 6 5 4 3 2 1 0 T3CNT7 T3CNT6 T3CNT5 T3CNT4 T3CNT3 T3CNT2 T3CNT1 T3CNT0 R R R R R R R R Initial value 00H T3CNT 7 0 T3 Counter T3DR Timer 3 Data Register Write Case 1001H ESFR 7 6 5 4 3 2 1 0 T3DR7 T3DR6 T3DR5 T3DR4 T3DR3 T3DR2 T3DR1 T3DR0 W W W W W W W W Initial value FFH T3DR 7 0 T3 Data T3CAPR Timer 3 Capture Data Register Read Case Capture mode only 1001H ESFR ...

Page 161: ...at match 1 Capture mode the match interrupt can occur T3CK 2 0 Select Timer 3 clock source fx is main system clock frequency T3CK2 T3CK1 T3CK0 Description 0 0 0 fx 2 0 0 1 fx 4 0 1 0 fx 8 0 1 1 fx 32 1 0 0 fx 128 1 0 1 fx 512 1 1 0 fx 2048 1 1 1 External Clock EC3 T3CN Control Timer 3 Count Pause Continue 0 Temporary count stop 1 Continue count T3ST Control Timer 3 Start Stop 0 Counter stop 1 Clea...

Page 162: ...nd timer 4 interrupt mask register T4MSK 11 8 12 Register Description for Timer Counter 4 T4PPRH Timer 4 PWM Period High Register 6 ch PWM mode only 1009H ESFR 7 6 5 4 3 2 1 0 T4PPRH1 T4PPRH0 R W R W Initial value 00H T4PPRH 1 0 T4 PWM Period Data High Byte T4PPRL Timer 4 PWM Period Low Register 6 ch PWM mode only 1008H ESFR 7 6 5 4 3 2 1 0 T4PPRL7 T4PPRL6 T4PPRL5 T4PPRL4 T4PPRL3 T4PPRL2 T4PPRL1 T...

Page 163: ...imer 4 PWM C Duty Low Register 6 ch PWM mode only 100EH ESFR 7 6 5 4 3 2 1 0 T4CDRL7 T4CDRL6 T4CDRL5 T4CDRL4 T4CDRL3 T4CDRL2 T4CDRL1 T4CDRL0 R W R W R W R W R W R W R W R W Initial value 7FH T4CDRL 7 0 T4 PWM C Duty Data Low Byte T4DLYA Timer 4 PWM A Delay Register 6 ch PWM mode only 1010H ESFR 7 6 5 4 3 2 1 0 T4DLYAA3 T4DLYAA2 T4DLYAA1 T4DLYAA0 T4DLYAB3 T4DLYAB2 T4DLYAB1 T4DLYAB0 R W R W R W R W ...

Page 164: ...nd Capture mode only 1013H ESFR 7 6 5 4 3 2 1 0 T4DR7 T4DR6 T4DR5 T4DR4 T4DR3 T4DR2 T4DR1 T4DR0 R W R W R W R W R W R W R W R W Initial value FFH T4DR 7 0 T4 Data T4CAPR Timer 4 Capture Data Register Read Case Capture mode only 1014H ESFR 7 6 5 4 3 2 1 0 T4CAPR7 T4CAPR6 T4CAPR5 T4CAPR4 T4CAPR3 T4CAPR2 T4CAPR1 T4CAPR0 R R R R R R R R Initial value 00H T4CAPR 7 0 T4 Capture Data T4CNT Timer 4 Counte...

Page 165: ...apture mode the match interrupt can occur T4CN Control Timer 4 Count Pause Continue 0 Temporary count stop 1 Continue count T4ST Control Timer 4 Start Stop 0 Counter stop 1 Clear counter and start T4CK 3 0 Select Timer 4 clock source fx is main system clock frequency T4CK3 T4CK2 T4CK1 T4CK0 Description 0 0 0 0 fx 1 0 0 0 1 fx 2 0 0 1 0 fx 4 0 0 1 1 fx 8 0 1 0 0 fx 16 0 1 0 1 fx 32 0 1 1 0 fx 64 0 ...

Page 166: ...NK input pin Where x A B and C BMOD Control Back to Back Mode Operation 0 Disable back to back mode up count only 1 Enable back to back mode up down count only PHLT Control Timer 4 PWM Operation 0 Run 10 bit PWM 1 Stop 10 bit PWM counter hold and output disable UPDT Select the Update Timer of T4PPR T4ADR T4BDR T4CDR 0 Update at period match of T4CNT and T4PPR 1 Update at any time when written UALL...

Page 167: ...M4xB pins are output according to the only T4ADR registers Where x A B and C PAAOE Select Channel PWM4AA Operation 0 Disable PWM4AA output 1 Enable PWM4AA output PABOE Select Channel PWM4AB Operation 0 Disable PWM4AB output 1 Enable PWM4AB output PBAOE Select Channel PWM4BA Operation 0 Disable PWM4BA output 1 Enable PWM4BA output PBBOE Select Channel PWM4BB Operation 0 Disable PWM4BB output 1 Enab...

Page 168: ...ing when disable POLAB POLBB POLCB bits where x A B and C POLAA Configure PWM4AA Channel Polarity 0 Start at high level This pin is low level when disable 1 Start at low level This pin is high level when disable POLAB Configure PWM4AB Channel Polarity 0 Non inversion signal of PWM4AA pin 1 Inversion signal of PWM4AA pin POLBA Configure PWM4BA Channel Polarity 0 Start at high level This pin is low ...

Page 169: ... no occurrence 1 PWM B ch match occurrence ICMC Timer 4 PWM C ch Match Interrupt Status Write 0 to this bit for clear 0 PWM C ch match no occurrence 1 PWM C ch match occurrence T4MSK Timer 4 Interrupt Mask Register 1007H ESFR 7 6 5 4 3 2 1 0 OVRMSK BTMMSK CMAMSK CMBMSK CMCMSK R W R W R W R W R W Initial value 00H OVRMSK Control Timer 4 compare match or Overflow Interrupt 0 Disable compare match or...

Page 170: ...ock divided by prescaler BUZDR 7 0 Buzzer Frequency kHz BUZCR 2 1 00 BUZCR 2 1 01 BUZCR 2 1 10 BUZCR 2 1 11 0000_0000 125kHz 62 5kHz 31 25kHz 15 625kHz 0000_0001 62 5kHz 31 25kHz 15 625kHz 7 812kHz 1111_1101 492 126Hz 246 063Hz 123 031Hz 61 515Hz 1111_1110 490 196Hz 245 098Hz 122 549Hz 61 274Hz 1111_1111 488 281Hz 244 141Hz 122 07Hz 61 035Hz Table 11 15 Buzzer Frequency at 8 MHz 11 9 2 Block Diagr...

Page 171: ...or Buzzer Driver BUZDR Buzzer Data Register 8FH 7 6 5 4 3 2 1 0 BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 R W R W R W R W R W R W R W R W Initial value FFH BUZDR 7 0 This bits control the Buzzer frequency Its resolution is 00H FFH BUZCR Buzzer Control Register 97H 7 6 5 4 3 2 1 0 BUCK1 BUCK0 BUZEN R W R W R W Initial value 00H BUCK 1 0 Buzzer Driver Source Clock Selection BUCK1 BUCK0...

Page 172: ...rt master slave mode can select serial clock SCK2 polarity phase and whether LSB first data transfer or MSB first data transfer 11 10 2 Block Diagram P r e s c a l e r fx M U X fx 4 fx 8 fx 32 fx 64 fx 128 fx 16 fx 2 SCK Control MS SCK2 3 SPICR 2 0 M U X MS CPHA Edge Detector CPOL SPI Control Circuit WCOL SPIEN INT_ACK Clear To interrupt block SPIIFR 8 bit Shift Register M U X MS SPIDR 8 bit FLSB ...

Page 173: ...4 SS2 pin function 1 When the SPI 2 is configured as a Slave the SS2 pin is always input If LOW signal comes into SS2 pin the SPI 2 logic is active And if HIGH signal comes into SS2 pin the SPI 2 logic is stop In this time SPI 2 logic will be reset and invalidated any received data 2 When the SPI 2 is configured as a Master the user can select the direction of the SS2 pin by port direction registe...

Page 174: ...put D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SCK2 CPOL 0 SS2 SPIIFR Figure 11 50 SPI 2 Transmit Receive Timing Diagram at CPHA 0 SCK2 CPOL 1 MISO2 MOSI2 Output MOSI2 MISO2 Input D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SCK2 CPOL 0 SS2 SPIIFR Figure 11 51 SPI 2 Transmit Receive Timing Diagram at CPHA 1 ...

Page 175: ... Map 11 10 7 SPI 2 Register Description The SPI 2 register consists of SPI 2 control register SPICR SPI 2 status register SPISR and SPI 2 data register SPIDR 11 10 8 Register Description for SPI 2 SPIDR SPI 2 Data Register B6H 7 6 5 4 3 2 1 0 SPIDR7 SPIDR6 SPIDR5 SPIDR4 SPIDR3 SPIDR2 SPIDR1 SPIDR0 R W R W R W R W R W R W R W R W Initial value 00H SPIDR 7 0 SPI 2 Data When it is written a byte to t...

Page 176: ...ect 0 SPI 2 Interrupt no generation 1 SPI 2 Interrupt generation WCOL This bit is set if any data are written to the data register SPIDR during transfer This bit is cleared when the status register SPISR is read and then access read write the data register SPIDR 0 No collision 1 Collision SS_HIGH When the SS2 pin is configured as input if HIGH signal comes into the pin this flag bit will be set 0 ...

Page 177: ...his two bits control the serial clock SCK2 mode Clock polarity CPOL bit determine SCK2 s value at idle mode Clock phase CPHA bit determine if data are sampled on the leading or trailing edge of SCK2 CPOL CPHA Leading edge Trailing edge 0 0 Sample Rising Setup Falling 0 1 Setup Rising Sample Falling 1 0 Sample Falling Setup Rising 1 1 Setup Falling Sample Rising DSCR SCR 2 0 These three bits select...

Page 178: ...ould be set to xxx The register ADCDRH and ADCDRL contains the results of the A D conversion When the conversion is completed the result is loaded into the ADCDRH and ADCDRL the A D conversion status bit AFLAG is set to 1 and the A D interrupt is set During A D conversion AFLAG bit is read as 0 11 11 2 Conversion Timing The A D conversion process requires 4 steps 4 clock edges to convert each bit ...

Page 179: ...SS AN1 AN2 AN14 AN15 ADCIFR AFLAG INT_ACK Clear Clear To interrupt block MUX VDD Start M U X T4 A match event signal T4 B match event signal T4 C match event signal REFSEL TRIG 2 0 3 ADST T1 A match signal T4 overflow event signal Figure 11 52 12 bit ADC Block Diagram Figure 11 53 A D Analog Input Pin with Capacitor AVREF Analog Power Input 22uF Figure 11 54 A D Power AVREF Pin with Capacitor 0 10...

Page 180: ... ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 Align bit set 1 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0 ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCDRL 7 0 ADCDRL 3 0 ADCDRL 7 4 bits are 0 ADCDRH 7 0 ADCDRL 7 4 ADCDRL 3 0 bits are 0 Figure 11 55 ADC Operation for Align Bit ...

Page 181: ...ter Table 11 18 ADC Register Map 11 11 6 ADC Register Description The ADC register consists of A D converter data high register ADCDRH A D converter data low register ADCDRL A D converter control high register ADCCRH and A D converter control low register ADCCRL SET ADCCRH SET ADCCRL AFLAG 1 Converting START READ ADCDRH L ADC END Select ADC Clock and Data Align Bit ADC enable Select AN Input Chann...

Page 182: ...D Converter High Register 9DH 7 6 5 4 3 2 1 0 ADCIFR TRIG2 TRIG1 TRIG0 ALIGN CKSEL1 CKSEL0 R W R W R W R W R W R W R W Initial value 00H ADCIFR When ADC interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 ADC Interrupt no generation 1 ADC Interrupt generation TRIG 2 0 A D Trigger Signal Selection TRIG2 TRIG1 TRIG0 Descr...

Page 183: ... ADC Conversion Start and auto clear REFSEL A D Converter Reference Selection 0 Internal Reference VDD 1 External Reference AVREF AFLAG A D Converter Operation State This bit is cleared to 0 when the STBY bit is set to 0 or when the CPU is at STOP mode 0 During A D Conversion 1 A D Conversion finished ADSEL 3 0 A D Converter input selection ADSEL3 ADSEL2 ADSEL1 ADSEL0 Description 0 0 0 0 AN0 0 0 0...

Page 184: ...us register 1 2 USI baud rate generation register USI data register USI SDA hold time register USI SCL high period register USI SCL low period register and USI slave address register USInCR1 USInCR2 USInCR3 USInCR4 USInST1 USInST2 USInBD USInDR USInSDHR USInSCHR USInSCLR USInSAR n is 0 or 1 The operation mode is selected by the operation mode of USIn selection bits USInMS 1 0 It has four operating...

Page 185: ... generator transmitter and receiver The clock generation logic consists of synchronization logic for external clock input used by synchronizing or SPI slave operation and the baud rate generator for asynchronous or master synchronous or SPI operation The Transmitter consists of a single write buffer a serial shift register parity generator and control logic for handling different serial frame form...

Page 186: ...t Shift Register TXSR USInDR USInTX8 Tx USInP 1 0 M U X LOOPSn TXCn TXCIEn DRIEn DREn Empty signal To interrupt block INT_ACK Clear RXCn RXCIEn WAKEIEn WAKEn At Stop mode To interrupt block SCLK fx System clock Low level detector 2 USInS 2 0 3 USInS 2 0 3 TXEn RXEn DBLSn USInSB Baud Rate Generator USInBD I N T E R N A L B U S L I N E SCKn ACK Control Clock Sync Logic Master USInMS 1 0 M U X M U X ...

Page 187: ...chronous double speed mode is controlled by the DBLSn bit in the USInCR2 register The MASTERn bit in USInCR3 register controls whether the clock source is internal master mode output pin or external slave mode input pin The SCKn pin is active only when the USIn operates in synchronous or SPI mode Following table shows the equations for calculating the baud rate in bps Operating Mode Equation for C...

Page 188: ... When synchronous or SPI mode is used the SCKn pin will be used as either clock input slave or clock output master Data sampling and transmitter is issued on the different edge of SCKn clock each other For example if data input on RXDn MISOn in SPI mode pin is sampled on the rising edge of SCKn clock data output on TXDn MOSIn in SPI mode pin is altered on the falling edge The CPOLn bit in USInCR1 ...

Page 189: ...stop bit A high to low transition on data pin is considered as start bit When a complete frame is transmitted it can be directly followed by a new frame or the communication line can be set to an idle state The idle means high state of data pin The following figure shows the possible combinations of the frame formats Bits inside brackets are optional Figure 11 60 Frame Format USIn 1 data frame con...

Page 190: ...it will transfer one complete frame according to the settings of control registers If the 9 bit characters are used in asynchronous or synchronous operation mode the ninth bit must be written to the USInTX8 bit in USInCR3 register before it is loaded to the transmit buffer USInDR register 11 12 9 2 USIn UART Transmitter flag and interrupt The USART transmitter has two flags which indicate its stat...

Page 191: ...Sn input pin in slave mode or can be configured as SSn output pin in master mode This can be done by setting USInSSEN bit in USInCR3 register 11 12 10 1 USIn UART Receiving RX data When UART is in synchronous or asynchronous operation mode the receiver starts data reception when it detects a valid start bit LOW on RXD0 pin Each bit after start bit is sampled at pre defined baud rate asynchronous o...

Page 192: ... The FEn flag is 0 when the stop bit was correctly detected as 1 and the FEn flag is 1 when the stop bit was incorrect i e detected as 0 This flag can be used for detecting out of sync conditions between data frames The data overrun DORn flag indicates data loss due to a receive buffer full condition DORn occurs when the receive buffer is full and another new data is presented in the receive shift...

Page 193: ...m and this removing the noise of RXDn pin The next figure illustrates the sampling process of the start bit of an incoming frame The sampling rate is 16 times of the baud rate in normal mode and 8 times the baud rate for double speed mode DBLSn 1 The horizontal arrows show the synchronization variation due to the asynchronous sampling process Note that larger time variation is shown when using the...

Page 194: ...eived bit is considered to a logic 0 and if more than 2 samples have high levels the received bit is considered to a logic 1 The data recovery process is then repeated until a complete frame is received including the first stop bit The decided bit value is stored in the receive shift register in order Note that the Receiver only uses the first stop bit of a frame Internally after receiving the fir...

Page 195: ...MOSIn for compatibility to other SPI devices 11 12 12 USIn SPI Clock Formats and Timing To accommodate a wide variety if synchronous serial peripherals from different manufacturers the USIn has a clock polarity bit CPOLn and a clock phase control bit CPHAn to select one of four clock formats for data transfers CPOLn selectively insert an inverter in series with the clock CPHAn selects one of two d...

Page 196: ... inputs respectively At the second SCKn edge the USIn shifts the second data bit value out to the MOSIn and MISOn outputs of the master and slave respectively Unlike the case of CPHAn 1 when CPHAn 0 the slave s SSn input must go to its inactive high level between transfers This is because the slave can prepare the first data bit when it detects falling edge of SSn input SCKn CPOLn 1 MISOn MOSIn SC...

Page 197: ... the MOSIn and MISOn output of the master and slave respectively When CPHAn 1 the slave s SSn input is not required to go to its inactive high level between transfers Because the SPI logic reuses the USIn resources SPI mode of operation is similar to that of synchronous or asynchronous operation An SPI transfer is initiated by checking for the USIn Data Register Empty flag DREn 1 and then writing ...

Page 198: ...DR Tx I N T E R N A L B U S L I N E M U X LOOPSn TXCn TXCIEn DRIEn DREn Empty signal To interrupt block INT_ACK Clear RXCn Baud Rate Generator USInBD TXEn SCLK fx System clock MISOn MOSIn M U X MASTERn D E P FXCHn SCKn SCK Control MASTERn RXEn To interrupt block M U X Edge Detector And Controller SSn SS Control CPHAn CPOLn ORDn MSB LSB 1st USInDR 1 Rx USInSSEN Figure 11 66 USIn SPI Block Diagram n...

Page 199: ...I2C bus standard Multi master operation Up to 400kHz data transfer read speed 7 bit address Both master and slave operation Bus busy detection 11 12 15 USIn I2C Bit Transfer The data on the SDAn line must be stable during HIGH period of the clock SCLn The HIGH or LOW state of the data line can only change when the clock signal on the SCLn line is LOW The exceptions are START S repeated START Sr an...

Page 200: ...T and repeated START conditions are functionally identical Figure 11 68 START and STOP Condition USIn 11 12 17 USIn I2C Data Transfer Every byte put on the SDAn line must be 8 bits long The number of bytes that can be transmitted per transfer is unlimited Each byte has to be followed by an acknowledge bit Data is transferred with the most significant bit MSB first If a slave can t receive or trans...

Page 201: ... Bus USIn 11 12 19 USIn I2C Synchronization Arbitration Clock synchronization is performed using the wired AND connection of I2C interfaces to the SCLn line This means that a HIGH to LOW transition on the SCLn line will cause the devices concerned to start counting off their LOW period and it will hold the SCLn line in that state until the clock HIGH state is reached However the LOW to HIGH transi...

Page 202: ...terrupt source bits in the USInST2 register are cleared to 0b When I2C interrupt occurs the SCLn line is hold LOW until clearing 0b all interrupt source bits in USInST2 register When the IICnIFR flag is set the USInST2 contains a value indicating the current state of the I2C bus According to the value in USInST2 software can decide what to do next I2C can operate in 4 modes by configuring master s...

Page 203: ...ice When I2C loses bus mastership during arbitration process the MLOSTn bit in USInST2 is set and I2C waits in idle state or can be operate as an addressed slave To operate as a slave when the MLOSTn bit in USInST2 is set the ACKnEN bit in USInCR4 must be set and the received 7 bit address must equal to the USInSLA 6 0 bits in USInSAR In this case I2C operates as a slave transmitter or a slave rec...

Page 204: ...DR 2 Master stops data transfer even if it receives ACK signal from slave In this case set the STOPCn bit in USInCR4 3 Master transmits repeated START condition with not checking ACK signal In this case load SLAn R W into the USInDR and set the STARTCn bit in USInCR4 After doing one of the actions above clear to 0b all interrupt source bits in USInST2 to release SCLn line In case of 1 move to step...

Page 205: ...ce When I2C loses bus mastership during arbitration process the MLOSTn bit in USInST2 is set and I2C waits in idle state or can be operate as an addressed slave To operate as a slave when the MLOSTn bit in USInST2 is set the ACKnEN bit in USInCR4 must be set and the received 7 bit address must equal to the USInSLA 6 0 bits in USInSAR In this case I2C operates as a slave transmitter or a slave rece...

Page 206: ...ause no ACK signal is detected master terminates data transfer In this case set the STOPCn bit in USInCR4 4 No ACK signal is detected and master transmits repeated START condition In this case load SLAn R W into the USInDR and set the STARTCn bit in USInCR4 After doing one of the actions above clear to 0b all interrupt source bits in USInST2 to release SCLn line In case of 1 and 2 move to step 7 I...

Page 207: ...er START condition Else if the address equals to USInSLA 6 0 bits and the ACKnEN bit is enabled I2C generates SSELn interrupt and the SCLn line is held LOW Note that even if the address equals to USInSLA 6 0 bits when the ACKnEN bit is disabled I2C enters idle state When SSELn interrupt occurs load transmit data to USInDR and clear to 0b all interrupt source bits in USInST2 to release SCLn line 5 ...

Page 208: ...TART condition Else if the address equals to SLAn bits and the ACKnEN bit is enabled I2C generates SSELn interrupt and the SCLn line is held LOW Note that even if the address equals to SLAn bits when the ACKnEN bit is disabled I2C enters idle state When SSELn interrupt occurs and I2C is ready to receive data clear to 0b all interrupt source bits in USInST2 to release SCLn line 5 Byte of data is be...

Page 209: ...x Slave Address Register USInSAR General Call And Address Detector USInGCE STOP START Condition Generator STOPCn STARTCn ACK Signal Generator ACKnEN RXACKn GCALLn TENDn STOPDn SSELn MLOSTn BUSYn TMODEn Interrupt Generator To interrupt block IICnIFR IICnIE NOTE 1 When the USIn block is an I2C mode and the corresponding port is a sub function for SCLn SDAn pin The SCLn SDAn pins are automatically se...

Page 210: ...ration Register USI1DR F5H R W 00H USI1 Data Register USI1SDHR F4H R W 01H USI1 SDA Hold Time Register USI1SCHR F7H R W 3FH USI1 SCL High Period Register USI1SCLR F6H R W 3FH USI1 SCL Low Period Register USI1SAR EDH R W 00H USI1 Slave Address Register USI1CR1 E9H R W 00H USI1 Control Register 1 USI1CR2 EAH R W 00H USI1 Control Register 2 USI1CR3 EBH R W 00H USI1 Control Register 3 USI1CR4 ECH R W ...

Page 211: ... mode NOTE 1 In common with USInSAR register USInBD register is used for slave address register when the USIn I2C mode USInDR USIn Data Register For UART SPI and I2C mode E5H F5H n 0 1 7 6 5 4 3 2 1 0 USInDR7 USInDR6 USInDR5 USInDR4 USInDR3 USInDR2 USInDR1 USInDR0 R W R W R W R W R W R W R W R W Initial value 00H USInDR 7 0 The USIn transmit buffer and receive buffer share the same I O address wit...

Page 212: ... The SDAn is changed after tSCLK X USInSDHR 2 in master mode So to insure operation in slave mode the value 4 tSCLK X USInSDHR 2 must be smaller than the period of SCL USInSCHR USInSCL High Period Register For I2C mode E7H F7H n 0 1 7 6 5 4 3 2 1 0 USInSCHR7 USInSCHR6 USInSCHR5 USInSCHR4 USInSCHR3 USInSCHR2 USInSCHR1 USInSCHR0 R W R W R W R W R W R W R W R W Initial value 3FH USInSCHR 7 0 This reg...

Page 213: ... SCLK the system clock and the period is calculated by the formula tSCLK X 4 X USInSCLR 2 where tSCLK is the period of SCLK USInSAR USIn Slave Address Register For I2C mode DDH EDH n 0 1 7 6 5 4 3 2 1 0 USInSLA6 USInSLA5 USInSLA4 USInSLA3 USInSLA2 USInSLA1 USInSLA0 USInGCE R W R W R W R W R W R W R W R W Initial value 00H USInSLA 6 0 These bits configure the slave address of I2C when it operates i...

Page 214: ...h of data bits in frame USInS2 USInS1 USInS0 Data Length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit ORDn This bit in the same bit position with USInS1 The MSB of the data byte is transmitted first when set to 1 and the LSB when set to 0 only SPI mode 0 LSB first 1 MSB first CPHAn This bit is in the same bit position with USInS0 This bit...

Page 215: ... RXCn is inhibited use polling 1 When RXCn is set request an interrupt WAKEIEn Interrupt enable bit for asynchronous wake in STOP mode When device is in stop mode if RXDn goes to low level an interrupt can be requested to wake up system only UART mode At that time the DRIEn bit and USInST1 register value should be set to 0b and 00H respectively 0 Interrupt from Wake is inhibited 1 When WAKEn is se...

Page 216: ...e UART is enabled in synchronous master mode 1 ACK is active while any frame is on transferring USInSSEN This bit controls the SSn pin operation only SPI mode 0 Disable 1 Enable The SSn pin should be a normal input FXCHn SPI port function exchange control bit only SPI mode 0 No effect 1 Exchange MOSIn and MISOn function USInSB Selects the length of stop bit in asynchronous or synchronous mode of o...

Page 217: ...nterrupt Enable bit for I2C mode 0 Interrupt from I2C is inhibited use polling 1 Enable interrupt for I2C ACKnEN Controls ACK signal Generation at ninth SCLn period 0 No ACK signal is generated SDAn 1 1 ACK signal is generated SDAn 0 NOTE ACK signal is output SDA 0 for the following 3 cases 1 When received address packet equals to USInSLA bits in USInSAR 2 When received address packet equals to va...

Page 218: ...rate a RXCn interrupt 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKEn This flag is set when the RXDn pin is detected low while the CPU is in STOP mode This flag can be used to generate a WAKEn interrupt This bit is set only when in asynchronous mode of operation This bit should be cleared by program software only UART mode 0 No WAKE interrup...

Page 219: ... condition is detected 1 STOP condition is detected SSELn This bit is set when I2C is addressed by other master 0 I2C is not selected as a slave 1 I2C is addressed by other master and acts as a slave MLOSTn This bit represents the result of bus arbitration in master mode 0 I2C maintains bus mastership 1 I2C maintains bus mastership during arbitration process BUSYn This bit reflects bus status 0 I2...

Page 220: ... bps fx 1 00MHz fx 1 8432MHz fx 2 00MHz USI0BD USI1BD ERROR USI0BD USI1BD ERROR USI0BD USI1BD ERROR 2400 25 0 2 47 0 0 51 0 2 4800 12 0 2 23 0 0 25 0 2 9600 6 7 0 11 0 0 12 0 2 14 4k 3 8 5 7 0 0 8 3 5 19 2k 2 8 5 5 0 0 6 7 0 28 8k 1 8 5 3 0 0 3 8 5 38 4k 1 18 6 2 0 0 2 8 5 57 6k 1 25 0 1 8 5 76 8k 1 0 0 1 18 6 115 2k 230 4k Baud Rate bps fx 8 00MHz USI0BD USI1BD ERROR 2400 207 0 2 4800 103 0 2 960...

Page 221: ...e LCD Control Register LCDCRH L The LCLK 1 0 determines the frequency of COM signal scanning of each segment output A RESET clears the LCD control register LCDCRH and LCDCRL values to logic 0 The LCD display can continue operating during IDLE and STOP modes if a sub frequency clock is used as LCD clock source ...

Page 222: ...ata and drive method Therefore display patterns can be changed by only overwriting the contents of the display external data area with a program Figure 11 99 shows the correspondence between the display external data area and the COM SEG pins The LCD is turned on when the display data is 1 and turned off when 0 SEG26 001AH SEG25 0019H SEG24 SEG23 SEG22 0016H SEG7 0007H SEG6 0006H SEG5 0005H SEG4 0...

Page 223: ... Frame VDD VSS 0 1 COM1 SEG1 COM0 SEG0 COM0 VSS VLC0 VLC2 VLC1 VLC3 COM0 COM1 SEG0 SEG1 SEG3 0 1 SEG2 SEG0 VSS VSS VLC0 VLC2 VLC1 VLC3 VLC2 VLC1 VLC3 VLC0 VSS VSS VLC0 VLC2 VLC1 VLC3 VLC0 VLC2 VLC1 VLC3 VLC0 VLC2 VLC1 VLC3 Figure 11 75 LCD Signal Waveforms 1 2Duty 1 2Bias ...

Page 224: ...Frame VDD VSS 0 1 COM1 SEG2 COM0 SEG1 COM0 VLC2 VLC3 VLC0 VLC1 SEG1 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 2 0 1 2 VSS VLC2 VLC3 VLC0 VLC1 VSS COM2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC1 VSS VLC0 VLC1 Figure 11 76 LCD Signal Waveforms 1 3Duty 1 3Bias ...

Page 225: ...ame VDD VSS 0 1 COM1 SEG3 COM0 SEG2 COM0 VLC2 VLC3 VLC0 VLC1 SEG2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 2 VSS VLC2 VLC3 VLC0 VLC1 VSS COM2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC1 VSS VLC0 VLC1 3 0 1 2 3 Figure 11 77 LCD Signal Waveforms 1 4Duty 1 3Bias ...

Page 226: ...G 9 S E G 1 0 1 Frame VDD VSS 0 COM1 SEG7 COM0 SEG6 COM0 VLC2 VLC0 VLC1 SEG6 VSS COM2 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC1 VLC3 VLC2 VLC0 Figure 11 78 LCD Signal Waveforms 1 8Duty 1 4Bias ...

Page 227: ...C1 VLC2 VLC3 LCTEN DISP VSS R VLC0 VLC1 VLC2 VLC3 VLCD 1 3 BIAS VLC0 VLC1 VLC2 VLC3 R Contrast Controller LCTEN DISP Contrast Controller LCTEN DISP Contrast Controller LCTEN DISP Contrast Controller R NOTE 1 The above figures are for the internal resistor bias connection So It is not needed an external connection 2 When the internal resistors are selected all the P40 VLC3 P41 VLC2 P42 VLC1 and P43...

Page 228: ...stors should be connected like the above figure and the needed bias pins should be selected as the LCD bias function pins VLC0 VLC1 VLC2 and VLC3 by P4FSR register 3 When it is 1 2 bias the P43 VLC0 and P41 VLC2 pins should be selected as VLC0 and VLC2 functions The other pins can be used for normal I O 4 When it is 1 3 bias the P43 VLC0 P42 VLC1 and P41 VLC2 pins should be selected as VLC0 VLC1 a...

Page 229: ... Block Diagram 11 13 6 Register Map Name Address Direction Default Description LCDCRH 9AH R W 00H LCD Driver Control High Register LCDCRL 99H R W 00H LCD Driver Control Low Register LCDCCR 9BH R W 00H LCD Contrast Control Register Table 11 23 LCD Register Map 11 13 7 LCD Driver Register Description LCD driver register has two control registers LCD driver control high register LCDCRH LCD driver con...

Page 230: ...ls are outputted through the P33 P30 NOTE 1 The COM0 COM1 COM2 COM3 signals can be outputted through the P33 P32 P31 P30 respectively 2 For example the COM0 signal may be outputted to P33 pin if the P3FSR 3 is 1b and the COMCHG bit is 1b 3 Refer to the port3 function selection register P3FSR 4 Available only below the 1 4 duty LCDDR LCD Driving Resistor for Bias Select 0 Internal LCD driving resis...

Page 231: ...2Bias RLCD 1 0 0 0 1 2Duty 1 2Bias 2xRLCD Other values Not available LCLK 1 0 LCD Clock Select When fWCK Watch timer clock 32 768kHz LCLK1 LCLK0 Description 0 0 fLCD 128Hz 0 1 fLCD 256Hz 1 0 fLCD 512Hz 1 1 fLCD 1024Hz NOTE 1 The LCD clock is generated by watch timer clock fWCK So the watch timer should be enabled when the LCD display is turned on LCD Clock Frequency fLCD LCD Frame Frequency fFRAME...

Page 232: ...16 28 step 0 1 0 0 VLC0 VDD x 16 27 step 0 1 0 1 VLC0 VDD x 16 26 step 0 1 1 0 VLC0 VDD x 16 25 step 0 1 1 1 VLC0 VDD x 16 24 step 1 0 0 0 VLC0 VDD x 16 23 step 1 0 0 1 VLC0 VDD x 16 22 step 1 0 1 0 VLC0 VDD x 16 21 step 1 0 1 1 VLC0 VDD x 16 20 step 1 1 0 0 VLC0 VDD x 16 19 step 1 1 0 1 VLC0 VDD x 16 18 step 1 1 1 0 VLC0 VDD x 16 17 step 1 1 1 1 VLC0 VDD x 16 16 step NOTE The LCD contrast step is...

Page 233: ...ock Timer0 4 Operates Continuously Halted Only when the Event Counter Mode is Enabled Timer operates Normally ADC Operates Continuously Stop BUZ Operates Continuously Stop SPI Operates Continuously Only operate with external clock USI0 1 Operates Continuously Only operate with external clock LCD Controller Operates Continuously Stop Can be operated with sub clock Internal OSC 16MHz Oscillation Sto...

Page 234: ...s and peripherals are operated normally but CPU stops It is released by reset or interrupt To be released by interrupt interrupt should be enabled before IDLE mode If using reset because the device becomes initialized state the registers have reset value Figure 12 1 IDLE Mode Release Timing by External Interrupt External Interrupt OSC Normal Operation Release CPU Clock Stand by Mode Normal Operati...

Page 235: ...ith the sub clock The source for exit from STOP mode is hardware reset and interrupts The reset re defines all the control registers When exit from STOP mode enough oscillation stabilization time is required to normal operation Figure 12 2 shows the timing diagram When released from STOP mode the Basic interval timer is activated on wake up Therefore before STOP instruction user must be set its re...

Page 236: ...he STOP mode is released by the interrupt which each interrupt enable flag 1 and the CPU jumps to the relevant interrupt service routine Even if the IE EA bit is cleared to 0 the STOP mode is released by the interrupt of which the interrupt enable flag is set to 1 Figure 12 3 STOP Mode Release Flow SET PCON 7 0 SET IEx b STOP Mode IEx b 1 Interrupt Request STOP Mode Release Y Interrupt Service Rou...

Page 237: ...ter 87H 7 6 5 4 3 2 1 0 PCON7 PCON3 PCON2 PCON1 PCON0 R W R W R W R W R W Initial value 00H PCON 7 0 Power Control 01H IDLE mode enable 03H STOP mode enable Other Values Normal operation NOTE 1 To enter IDLE mode PCON must be set to 01H 2 To enter STOP mode PCON must be set to 03H 3 The PCON register is automatically cleared by a release signal in STOP IDLE mode 4 Three or more NOP instructions mu...

Page 238: ...al Registers Table 13 1 Reset State 13 2 Reset Source The MC96F6432A has five types of reset sources The following is the reset sources External RESETB Power ON RESET POR WDT Overflow Reset In the case of WDTEN 1 Low Voltage Reset In the case of LVREN 0 13 3 RESET Block Diagram Figure 13 1 RESET Block Diagram WDT RST WDT RSTEN Ext RESET Disable by FUSE RESET Noise Canceller LVR LVR Enable RESET No...

Page 239: ...the POR Power On Reset has a function to reset the device If POR is used it executes the device RESET function instead of the RESET IC or the RESET circuits Figure 13 3 Fast VDD Rising Time Figure 13 4 Internal RESET Release Timing On Power Up t TRNC t TRNC t TRNC t TRNC t TRNC A A VDD nPOR Internal Signal Internal RESETB Oscillation BIT Starts BIT Overflows Fast VDD Rise Time max 30 0V ms VDD nPO...

Page 240: ...RESETB BIT for Configure LVR_RESETB BIT for Reset INT OSC 8 MHz 8 INT OSC 8 MHz RESET_SYSB Configure Read 1us X 256 X 28h about 10ms 1us X 4096 X 4h about 16ms 00 01 02 03 00 27 28 F1 Counting for configure read start after POR is released H INT OSC 8MHz 8 1MHz 1us 00 01 01 02 03 04 05 00 Reset Release Configure Read POR VDD Input Internal OSC ...

Page 241: ...Configure option read Slew Rate 0 05V ms Configure option read point about 1 5V 1 6V Configure Value is determined by Writing Option Rising section to Reset Release Level 16ms point after POR or Ext_reset release Reset Release section BIT overflow i after 16ms after External Reset Release External reset ii 16ms point after POR POR only BIT is used for Peripheral stability Normal operation Table 13...

Page 242: ...ternal RESET becomes 1 The Reset process step needs 5 oscillator clocks And the program execution starts at the vector address stored at address 0000H Figure 13 7 Timing Diagram after RESET Figure 13 8 Oscillator generating waveform example NOTE 1 As shown Figure 13 8 the stable generating time is not included in the start up time 2 The RESETB pin has a Pull up register by hardware OSC ADDRESS BUS...

Page 243: ... 59V 2 75V 2 93V 3 14V 3 38V 3 67V 4 00V 4 40V In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consumption the LVREN bit is set to off by software Figure 13 9 Block Diagram of BOD Figure 13 10 Internal Reset at the power fail situation LVRVS 3 0 RESET_BODB Brown Out Detector BOD D Q CP r External VDD LVREN LVRF Low Voltage Reset Flag ...

Page 244: ...ng when BOD RESET VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset INT OSC 8MHz 8 INT OSC 8MHz RESET_SYSB Config Read 1us X 256 X 28h about 10ms 1us X 4096 X 4h about 16ms F1 00 01 02 00 27 28 F1 H INT OSC 8MHz 8 1MHz 1us H H Main OSC Off 01 02 03 04 00 ...

Page 245: ...ter Map Name Address Direction Default Description RSTFR E8H R W 80H Reset Flag Register LVRCR D8H R W 00H Low Voltage Reset Control Register LVICR 86H R W 00H Low Voltage Indicator Control Register Table 13 3 Reset Operation Register Map 13 10 Reset Operation Register Description The reset control register consists of the reset flag register RSTFR low voltage reset control register LVRCR and low ...

Page 246: ...his bit or by Power On Reset 0 No detection 1 Detection LVRF Low Voltage Reset flag bit The bit is reset by writing 0 to this bit or by Power On Reset 0 No detection 1 Detection NOTE 1 When the Power On Reset occurs the PORF bit is only set to 1 the other flag WDTRF bits are all cleared to 0 2 When the Power On Reset occurs the EXTRF bit is unknown At that time the EXTRF bit can be set to 1 when E...

Page 247: ...mode to release LVRVS 3 0 LVR Voltage Select LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description 0 0 0 0 1 85V 0 0 0 1 2 20V 0 0 1 0 2 20V 0 0 1 1 2 20V 0 1 0 0 2 32V 0 1 0 1 2 44V 0 1 1 0 2 59V 0 1 1 1 2 75V 1 0 0 0 2 93V 1 0 0 1 3 14V 1 0 1 0 3 38V 1 0 1 1 3 67V 1 1 0 0 4 00V 1 1 0 1 4 40V 1 1 1 0 Not available 1 1 1 1 Not available LVREN LVR Operation 0 LVR Enable 1 LVR Disable NOTE 1 The LVRST LVRVS 3 0 b...

Page 248: ...0H LVIF Low Voltage Indicator Flag Bit 0 No detection 1 Detection LVIEN LVI Enable Disable 0 Disable 1 Enable LVILS 3 0 LVI Level Select LVILS3 LVILS2 LVILS1 LVILS0 Description 0 0 0 0 2 20V 0 0 0 1 2 20V 0 0 1 0 2 20V 0 0 1 1 2 32V 0 1 0 0 2 44V 0 1 0 1 2 59V 0 1 1 0 2 75V 0 1 1 1 2 93V 1 0 0 0 3 14V 1 0 0 1 3 38V 1 0 1 0 3 67V 1 0 1 1 4 00V 1 1 0 0 4 40V Other Values Not available ...

Page 249: ...equipped with on chip debugger We recommend to develop and debug program with MC96F6432 On chip debug system of MC96F6432 can be used for programming the non volatile memories and on chip debugging Detail descriptions for programming via the OCD interface can be found in the following chapter Figure 14 1 shows a block diagram of the OCD interface and the On chip Debug system ...

Page 250: ... Including Break Instruction Single Step Break Program Memory Break Points on Single Address Programming of Flash EEPROM Fuses and Lock Bits through the two wire Interface On chip Debugging Supported by Dr Choice Operating frequency Supports the maximum frequency of the target MCU Figure 14 1 Block Diagram of On Chip Debug System BDC Format converter USB CPU Code memory SRAM Flash EEPROM Data memo...

Page 251: ...ge bit as 0 when transmission for 8 bit data and its parity has no error When transmitter has no acknowledge Acknowledge bit is 1 at tenth clock error process is executed in transmitter When acknowledge error is generated host PC makes stop condition and transmits command which has error again Background debugger command is composed of a bundle of packet Start condition and stop condition notify t...

Page 252: ...4 3 Data Transfer on the Twin Bus 14 2 2 2 Bit Transfer Figure 14 4 Bit Transfer on the Serial Bus St Sp START STOP DSDA DSCL LSB acknowledgement signal from receiver ACK ACK 1 10 1 10 acknowledgement signal from receiver LSB data line stable data valid except Start and Stop change of data allowed DSDA DSCL ...

Page 253: ...rocedure St Sp START condition STOP condition DSDA DSCL DSDA DSCL 1 9 2 10 Data output By transmitter Data output By receiver DSCL from master clock pulse for acknowledgement no acknowledge acknowledge Start wait start HIGH Host PC DSCL OUT Target Device DSCL OUT DSCL wait HIGH Maximum 5 TSCLK Internal Operation Acknowledge bit transmission minimum 1 TSCLK for next byte transmission Acknowledge bi...

Page 254: ...idirectional I O Figure 14 8 Connection of Transmission DSCL OUT DSDA OUT DSDA IN DSCL Debugger Serial Clock Line DSDA Debugger Serial Data Line DSDA OUT DSDA IN Host Machine Master Target Device Slave VDD VDD Current source for DSCL to fast 0 to 1 transition in high speed mode pull up resistors Rp Rp VDD DSCL IN DSCL OUT DSCL IN ...

Page 255: ...an be read by MOVC instruction and it can be programmed in serial ISP mode or user program mode Flash Size 32Kbytes Single power supply program and erase Command interface for fast program and erase operation Up to 100 000 Sector 0 507 100 000 Sector 508 511 program erase cycles at typical voltage and temperature for flash memory NOTE 1 The RXE bit of USInCR2 register should be disabled before fla...

Page 256: ...7F80H 07F7FH 07F40H Sector 509 07F40H 07F3FH Sector 508 Sector 2 00080H 0007FH 00040H Sector 1 00040H 0003FH 00000H Sector 0 00000H 00080H 8000H 803FH ROM Address Accessed by MOVX instruction only Page Sector Buffer Address Flash Controller FSADRH M L FIDR FMCR 64bytes Flash Page Buffer External Data Memory 64bytes Figure 15 1 Flash Program ROM Structure ...

Page 257: ...Flash Identification Register FMCR FEH R W 00H Flash Mode Control Register Table 15 1 Flash Memory Register Map 15 1 4 Register Description for Flash Memory Control and Status Flash control register consists of the flash sector address high register FSADRH flash sector address middle register FSADRM flash sector address low register FSADRL flash identification register FIDR and flash mode control ...

Page 258: ...al value 00H FSADRM 7 0 Flash Sector Address Middle FSADRL Flash Sector Address Low Register FCH 7 6 5 4 3 2 1 0 FSADRL7 FSADRL6 FSADRL5 FSADRL4 FSADRL3 FSADRL2 FSADRL1 FSADRL0 R W R W R W R W R W R W R W R W Initial value 00H FSADRL 7 0 Flash Sector Address Low FIDR Flash Identification Register FDH 7 6 5 4 3 2 1 0 FIDR7 FIDR6 FIDR5 FIDR4 FIDR3 FIDR2 FIDR1 FIDR0 R W R W R W R W R W R W R W R W In...

Page 259: ...rupt is on disable state regardless of the IE 7 EA bit FMCR2 FMCR1 FMCR0 Description 0 0 1 Select flash page buffer reset mode and start regardless of the FIDR value Clear all 64bytes to 0 0 1 0 Select flash sector erase mode and start operation when the FIDR 10100101b 0 1 1 Select flash sector write mode and start operation when the FIDR 10100101b 1 0 0 Select flash sector Code Write Protection a...

Page 260: ...nable protection area at the configure option 2 if it is needed If the protection area isn t enabled PAEN 1 this area can be used as a normal program memory The size of protection area can be varied by setting of configure option 2 Protection Area Size Select Size of Protection Area Address of Protection Area PASS2 PASS1 PASS0 0 0 0 0 7Kbytes 0100H 0FFFH 0 0 1 1 7Kbytes 0100H 07FFH 0 1 0 2 7Kbytes...

Page 261: ...ction This instruction must be needed NOP Dummy instruction This instruction must be needed MOV A 0 MOV R0 SectorSize Sector size of Device MOV DPH 0x80 Page Buffer Address is 8000H MOV DPL 0 Pgbuf_clr MOVX DPTR A INC DPTR DJNZ R0 Pgbuf_clr Write 0 to all page buffer MOV FSADRH SAH Sector Address High Byte MOV FSADRM SAM Sector Address Middle Byte MOV FSADRL SAL Sector Address Low Byte MOV FIDR 0x...

Page 262: ...on must be needed NOP Dummy instruction This instruction must be needed NOP Dummy instruction This instruction must be needed MOV A 0 MOV R0 SectorSize Sector size of Device MOV DPH 0x80 Page Buffer Address is 8000H MOV DPL 0 Pgbuf_WR MOVX DPTR A INC A INC DPTR DJNZ R0 Pgbuf_WR Write data to all page buffer MOV FSADRH SAH Sector Address High Byte MOV FSADRM SAM Sector Address Middle Byte MOV FSADR...

Page 263: ...instruction must be needed NOP Dummy instruction This instruction must be needed NOP Dummy instruction This instruction must be needed MOV A 5 MOV DPH 0x80 MOV DPL 0 MOVX DPTR A Write data to page buffer MOV A 6 MOV DPH 0x80 MOV DPL 0x05 MOVX DPTR A Write data to page buffer MOV FSADRH SAH Sector Address High Byte MOV FSADRM SAM Sector Address Middle Byte MOV FSADRL SAL Sector Address Low Byte MOV...

Page 264: ...WriteErase MOV A ID_DATA_3 CJNE A UserID3 No_WriteErase MOV FMCR 0x 0x03 if write 0x02 if erase RET No_WriteErase MOV FIDR 00H MOV UserID1 00H MOV UserID2 00H MOV UserID3 00H MOV Flash_flag 00H RET If code is like the above lines an invalid flash erase write can be avoided NOTE On flash memory erase and write it should be disabled the RXE bit of USInCR2 register 2 It is important where the UserID1...

Page 265: ... Work2 CALL ID_write CALL Work3 CALL Flash_erase CALL Flash_write ID_wire MOV A 38H CJNE A Flash_flag1 No_write_ID MOV A 75H CJNE A Flash_flag2 No_write_ID MOV UserID1 ID_DATA_1 Write Uiser ID1 MOV A 38H CJNE A Flash_flag1 No_write_ID MOV A 75H CJNE A Flash_flag2 No_write_ID MOV UserID2 ID_DATA_2 Write Uiser ID2 MOV A 38H CJNE A Flash_flag1 No_write_ID MOV A 75H CJNE A Flash_flag2 No_write_ID MOV ...

Page 266: ...case for flash memory to be erased by malfunction noise and power off Figure 15 2 Flow of Protection for Invalid Erase Write Start Work1 Set Flags Write UserID1 2 3 Clear the Flag Clear UserID1 2 3 Write Erase Flash Work2 Work3 Decide to write erase on flash Check the flag for UserID Check the UserID for write erase flash Yes Match Match ...

Page 267: ...ck the UserID for to prevent the invalid work Note 3 Set flash mode control register FMCR NOTE Please refer to the chapter Protection for Invalid Erase Write Program Tip Code Write Protection MOV FIDR 0xA5 Identification value MOV A ID_DATA_1 Check the UserID written by user CJNE A UserID1 No_WriteErase This routine for UserID must be needed MOV A ID_DATA_2 CJNE A UserID2 No_WriteErase MOV FMCR 0x...

Page 268: ...y instruction RSTS Select RESETB pin 0 Disable RESETB pin P55 1 Enable RESETB pin CONFIGURE OPTION 1 ROM Address 003EH 7 6 5 4 3 2 1 0 PAEN PASS2 PASS1 PASS0 Initial value 00H PAEN Enable Specific Area Write Protection 0 Disable Protection Erasable by instruction 1 Enable Protection Not erasable by instruction PASS 2 0 Select Specific Area for Write Protection NOTE 1 When PAEN 1 it is applied PASS...

Page 269: ...ect byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 9F SUBB A dir Subtract direct byte from A with borrow 2 1 95 SUBB A Ri Subtract indirect memory from A with borrow 1 1 96 97 SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 IN...

Page 270: ...1 1 46 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 XRL A Rn Exclusive OR register to A 1 1 68 6F XRL A dir Exclusive OR direct byte to A 2 1 65 XRL A Ri Exclusive OR indirect memory to A 1 1 66 67 XRL A data Exclusive OR immediate to A 2 1 64 XRL dir A Exclusive OR A to direct byte 2 1 62 XRL dir data Exclusive OR imme...

Page 271: ... A DPTR Move code byte relative DPTR to A 1 2 93 MOVC A A PC Move code byte relative PC to A 1 2 83 MOVX A Ri Move external data A8 to A 1 2 E2 E3 MOVX A DPTR Move external data A16 to A 1 2 E0 MOVX Ri A Move A to external data A8 1 2 F2 F3 MOVX DPTR A Move A to external data A16 1 2 F0 PUSH dir Push direct byte onto stack 2 2 C0 POP dir Pop direct byte from stack 2 2 D0 XCH A Rn Exchange A and re...

Page 272: ...ompare register immediate jne relative 3 2 B8 BF CJNE Ri d rel Compare indirect immediate jne relative 3 2 B6 B7 DJNZ Rn rel Decrement register jnz relative 2 2 D8 DF DJNZ dir rel Decrement direct byte jnz relative 3 2 D5 MISCELLANEOUS Mnemonic Description Bytes Cycles Hex code NOP No operation 1 1 00 ADDITIONAL INSTRUCTIONS selected through EO 7 4 Mnemonic Description Bytes Cycles Hex code MOVC D...

Page 273: ... the flags in program and check the flags in main loop at the end When the Flash Erase Write is executed check the flags If not matched do not execute Check the range of Flash Sector Address If the flash sector address is outside of specific area do not execute Use the Dummy Address Set the flash sector address to dummy address in usually run time Change the flash sector address to real area range...

Page 274: ... Write Flash Set User_ID1 Working Check User_ID1 Set User_ID2 Working Check User_ID2 Set User_ID3 Working Yes Yes Yes No No No Write Flash Clear User_ID1 2 3 Clear FIDR Clear FMCR Set FSADRH M L to Dummy Addr Check User_ID1 2 3 Set FSADDRH M L Set FIDR Set FMCR Check LVI Yes Yes No No Check Flash Addr Min Max No Yes ...

Page 275: ...se Write in flash Set to Dummy address after Erase Write Even if invalid work occurred it will be Erase Write in Dummy address in flash Check Flags If every flag User_ID1 2 3 LVI Flash Address Min Max was set than do Erase Write If the Flash Sector Address is outside of Min Max do not execute Address Min Max is set to unused area Initialize Flags Initialize User_ID1 2 3 Set Flash Sector Address to...

Page 276: ...haracteristics 30 7 6 High Internal RC Oscillator Characteristics 30 7 7 Internal Watch Dog Timer RC Oscillator Characteristics 31 7 8 LCD Voltage Characteristics 31 7 9 DC Characteristics 32 7 10 AC Characteristics 33 7 11 SPI0 1 2 Characteristics 34 7 12 UART0 1 Characteristics 35 7 13 I2C0 1 Characteristics 36 7 14 Data Retention Voltage in Stop Mode 37 7 15 Internal Flash Rom Characteristics 3...

Page 277: ...rrupt Controller 81 10 1 Overview 81 10 2 External Interrupt 83 10 3 Block Diagram 84 10 4 Interrupt Vector Table 85 10 5 Interrupt Sequence 86 10 6 Effective Timing after Controlling Interrupt Bit 87 10 7 Multi Interrupt 88 10 8 Interrupt Enable Accept Timing 89 10 9 Interrupt Service Routine Address 89 10 10 Saving Restore General Purpose Registers 89 10 11 Interrupt Timing 90 10 12 Interrupt Re...

Page 278: ... Counter Mode 120 11 6 3 16 bit Capture Mode 122 11 6 4 16 bit PPG Mode 124 11 6 5 Block Diagram 126 11 6 6 Register Map 126 11 6 7 Timer Counter 1 Register Description 127 11 6 8 Register Description for Timer Counter 1 127 11 7 Timer 2 130 11 7 1 Overview 130 11 7 2 16 bit Timer Counter Mode 131 11 7 3 16 bit Capture Mode 133 11 7 4 16 bit PPG Mode 135 11 7 5 Block Diagram 137 11 7 6 Register Ma...

Page 279: ... 12 9 3 USIn UART Parity Generator 191 11 12 9 4 USIn UART Disabling Transmitter 191 11 12 10 USIn UART Receiver 191 11 12 10 1 USIn UART Receiving RX data 191 11 12 10 2 USIn UART Receiver Flag and Interrupt 192 11 12 10 3 USIn UART Parity Checker 192 11 12 10 4 USIn UART Disabling Receiver 192 11 12 10 5 USIn Asynchronous Data Reception 193 11 12 11 USIn SPI Mode 195 11 12 12 USIn SPI Clock Form...

Page 280: ...ption for Reset Operation 246 14 On chip Debug System MC96F6432 ONLY 249 14 1 Overview 249 14 1 1 Description 249 14 1 2 Feature 250 14 2 Two Pin External Interface 251 14 2 1 Basic Transmission Packet 251 14 2 2 Packet Transmission Timing 252 14 2 2 1 Data Transfer 252 14 2 2 2 Bit Transfer 252 14 2 2 3 Start and Stop Condition 253 14 2 2 4 Acknowledge Bit 253 14 2 3 Connection of Transmission 25...

Page 281: ...281 MC96F6432A ABOV Semiconductor Co Ltd 17 1 Instruction Table 269 17 2 Flash Protection for Invalid Erase Write 273 Table of contents 276 ...

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