201
MC96F6432A
ABOV Semiconductor Co., Ltd.
11.12.18
USIn I2C Acknowledge
The acknowledge related clock pulse is generated by the master. The transmitter releases the SDAn line (HIGH)
during the acknowledge clock pulse. The receiver must pull down the SDAn line during the acknowledge clock pulse
so that it remains stable LOW during the HIGH period of this clock pulse. When a slave is addressed by a master
(Address Packet) and if it is unable to receive or transmit because it
’s performing some real time function, the data line
must be left HIGH by the slave. And also, when a slave addressed by a master is unable to receive more data bits, the
slave receiver must release the SDAn line (Data Packet). The master can then generate either a STOP condition to
abort the transfer or a repeated START condition to start a new transfer.
If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an
acknowledge on the last byte that was clocked out of the slave. The slave transmitter must release the data line to
allow the master to generate a STOP or repeated START condition.
Figure 11.70
Acknowledge on the I2C-Bus (USIn)
11.12.19
USIn I2C Synchronization / Arbitration
Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCLn line. This means
that a HIGH to LOW transition on the SCLn line will cause the devices concerned to start counting off their LOW
period and it will hold the SCLn line in that state until the clock HIGH state is reached. However the LOW to HIGH
transition of this clock may not change the state of the SCLn line if another clock is still within its LOW period. In this
way, a synchronized SCLn clock is generated with its LOW period determined by the device with the longest clock
LOW period and its HIGH period determined by the one with the shortest clock HIGH period.
A master may start a transfer only if the bus is free. Two or more masters may generate a START condition. Arbitration
takes place on the SDAn line, while the SCLn line is at the HIGH level, in such a way that the master which transmits a
HIGH level, while another master is transmitting a LOW level will switch off its DATA output state because the level on
the bus doesn
’t correspond to its own level. Arbitration continues for many bits until a winning master gets the
ownership of I2C bus. Its first stage is comparison of the address bits.
1
2
8
Data Output
By Transmitter
9
ACK
NACK
Clock pulse for ACK
Data Output
By Receiver
SCLn From MASTER
Summary of Contents for MC96F6432A
Page 16: ...16 MC96F6432A ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 48 Pin QFN Package ...
Page 17: ...17 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 2 44 Pin MQFP Package ...
Page 18: ...18 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 3 32 Pin LQFP Package ...
Page 19: ...19 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 4 32 Pin SOP Package ...
Page 20: ...20 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 5 28 Pin SOP Package ...
