211
MC96F6432A
ABOV Semiconductor Co., Ltd.
11.12.24
Register Description for USIn
USInBD (USIn Baud- Rate Generation Register: For UART and SPI mode): E3H/F3H, n = 0, 1
7
6
5
4
3
2
1
0
USInBD7
USInBD6
USInBD5
USInBD4
USInBD3
USInBD2
USInBD1
USInBD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FFH
USInBD[7:0]
The value in this register is used to generate internal baud rate in asynchronous
mode or to generate SCKn clock in SPI mode. To prevent malfunction, do not write
‘0’ in asynchronous mode and do not write ‘0’ or ‘1’ in SPI mode.
NOTE)
1.
In common with USInSAR register, USInBD register is used for slave
address register when the USIn I2C mode.
USInDR (USIn Data Register: For UART, SPI and I2C mode): E5H/F5H, n = 0, 1
7
6
5
4
3
2
1
0
USInDR7
USInDR6
USInDR5
USInDR4
USInDR3
USInDR2
USInDR1
USInDR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
USInDR[7:0]
The USIn transmit buffer and receive buffer share the same I/O address with this
DATA register. The transmit data buffer is the destination for data written to the
USInDR register. Reading the USInDR register returns the contents of the receive
buffer.
Write to this register only when the DREn flag is set. In SPI master mode, the SCK
clock is generated when data are written to this register.
Summary of Contents for MC96F6432A
Page 16: ...16 MC96F6432A ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 48 Pin QFN Package ...
Page 17: ...17 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 2 44 Pin MQFP Package ...
Page 18: ...18 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 3 32 Pin LQFP Package ...
Page 19: ...19 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 4 32 Pin SOP Package ...
Page 20: ...20 MC96F6432A ABOV Semiconductor Co Ltd Figure 4 5 28 Pin SOP Package ...
