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I.L. 40-385.1B
1-4
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The 60 Hz components are extracted from the sam-
ples (from each cycle) and converted to voltage and
current phasor values using a Fourier notch-filter al-
gorithm. An additional dc-offset correction algorithm
reduces overreach errors from decaying exponential
transients. During the process, the sum of squares of
the inputs are accumulated to provide rms values of
current and voltage. The Fourier coefficients and
sums are calculated for computing the phase angles.
The sum of squares and the sums of the Fourier co-
efficients are updated for each sample, using infor-
mation from the previous seven samples, to provide
a full cycle of data.
1.5.2
Fault Mode and Restricted Fault Tests
Upon entry into the fault mode, the sums of the Fou-
rier coefficients and sum of squares from the back-
ground mode are stored. New sums are obtained,
using fault data, to which offset compensation has
been applied.
To speed up tripping for severe faults, restricted fault
testing is implemented. The last half cycle of back-
ground mode input samples and the first half cycle of
fault mode input samples are used to compute the
current and voltage vectors and rms values. No dc
offset compensation is performed. High-set instanta-
neous overcurrent and Zone 1 distance unit tests are
executed (see Section 3.2, MDAR Line Measure-
ment). This will speed up tripping by as much as one
cycle for high current faults.
Instantaneous overcurrent, inverse time overcurrent
protection, and out-of-step blocking are also con-
ducted during the fault mode and background mode.
For Zone 2 and Zone 3 faults (see Section 3), imped-
ance computation and checking will continue
throughout the specified time delay. The impedance
calculation will be performed once every cycle, in the
fault mode and background mode.
1.5.3
Unique Qualities of MDAR
A unique characteristic of the MDAR system is its
phase selection principle. It determines the sum of
positive and negative sequence currents for each
phase by a novel method which excludes the influ-
ence of pre-fault load current. From this information,
the fault type can be clearly identified and the actual
distance to the fault can be estimated.
High-resistance ground-fault detection is available in
MDAR. Sensitive directional pilot tripping is achieved
through an FDOG timer (FDGT), which is selectable
from 0 to 15 cycles or block, on the Microprocessor
module. The pilot distance unit is always active and
has the priority for tripping.
Load-loss tripping entails high-speed, essentially si-
multaneous clearing at both terminals of a transmis-
sion line for all fault types except three-phase,
without the need of a pilot channel.
Any fault location on the protected circuit will be with-
in the reach of the zone 1 relays at one or both ter-
minals. This causes direct tripping of the local
breaker without the need for any information from
the remote terminal. The remote terminal recognizes
the loss of load-current in the unfaulted phase(s) as
evidence of tripping of the remote breaker. This, cou-
pled with Zone 2 distance or directional overcurrent
ground fault recognition at that terminal, allows im-
mediate tripping to take place at that terminal.
1.6
SELF-CHECKING SOFTWARE
MDAR continually monitors its ac input subsystems
using multiple A/D converter calibration-check in-
puts, plus loss-of-potential and loss-of-current moni-
toring described. Failures of the converter, or any
problem in a single ac channel which unbalances
nonfault inputs, trigger alarms. Self-checking soft-
ware includes the following functions:
a. Digital Front-end A/D Converter Check
b. Program Memory Check Sum
Immediately upon power-up, the relay does a com-
plete ROM (EPROM) checksum of program memo-
ry. Afterwards, the MDAR relay continually
computes the program memory checksum.
c. Power Up RAM Check
Immediately upon power-up, the relay does a com-
plete ROM test of the RAM data memory.
d. Nonvolatile RAM Check
All front-panel-entered constants (settings) are
stored in nonvolatile RAM in three identical arrays.
These arrays are continuously checked by the pro-
gram. If all three array entrees disagree, a nonvola-
tile RAM failure is detected.
For failures which do not disable the processor, the
cause of the problem can be read on the display.
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Page 135: ...I L 40 385 1B SD 6 5 92 Figure SD 2 MDAR Block Diagram sheet 1 of 1 Sub 1 1611C12...