96 PPC11A 6U VME Single Board Computer
Publication No. PPC11A-HRM/1
5.29
Test Register (Offset 0x6C7)
Bits
Description
Default
7
Reserved
0
6
BMM I
2
C bus to sensor bus buffer enable:
1 = BMM I
2
C bus connected to sensor bus
0 = BMM I
2
C bus isolated from sensor bus
This is sticky when reset using BIT_HRESET or CPU_RESET_REQ_L
0
5
Trigger the clock synthesizer programmer to execute a program cycle to the clock synthesizer.
Write the sequence “1”, “0”, “0”, “1” using consecutive writes to start the cycle. This will cause a board reset
0
4
Test input to FPGA configuration memory error detector:
1 = Force error detector to flag an error at the end of the current cycle
0 = Do not force error
Setting this bit will cause the FPGA to reload and the PPC11A will reset
0
3
Processor I
2
C bus 2 to sensor bus buffer enable:
1 = Processor I
2
C bus 2 connected to sensor bus
0 = Processor I
2
C bus 2 isolated from sensor bus
This permits the processor to access the I
2
C sensor bus directly. It should only be enabled when the BMM is inactive.
It is sticky when reset using BIT_HRESET or CPU_RESET_REQ_L
0
2
Disable the PCIe switch EEPROM:
1 = Disable PCIe switch auto-loading from its EEPROM
0 = Enable PCIe switch EEPROM
Software can use this to prevent the PCIe switch from loading the configuration table stored in its private EEPROM.
It is sticky when reset using BIT_HRESET or CPU_RESET_REQ_L
0
1 & 0
Mezzanine sites override:
11
b
= Force PMC site
10
b
= Force XMC site
0x
b
= Enable auto detection
Test software can use this to override the automatic mezzanine detection logic.
It is sticky when reset using BIT_HRESET or CPU_RESET_REQ_L
00
