Publication No. PPC11A-HRM/1
Functional Description 33
4.4
SDRAM
The PPC11A provides one bank of nine DDR3L SDRAM devices connected to the
memory controller within the processor. The T2081/T1042 processors contain a 64-bit
DDR3 memory controller, which has full ECC error-correction support, with the
ability to detect single and two-bit errors and correct single-bit errors within a
nibble. The memory interface can operate at 1600 MT/s.
4.4.1 Capacity
The PPC11A provides 8 GB of SDRAM in a single bank, connected to a separate
memory controller. The RAM configuration is defined below:
Table 4-4 SDRAM Configuration
Quantity
Number of Devices
Device Type
Number of Ranks/Controller
8 GB
9
8 Gbit die-stack
2
The processor controls the frequency of the RAM interface;
possible configurations.
4.4.2 Serial Presence Detect
The PPC11A implements a mechanism like the JEDEC DDR3 SPD to indicate the
RAM layout and timing information to the system. The SPD uses a virtual I
2
C ROM
that is embedded within the FPGA.
4.5
NOR Flash
The PPC11A provides 512 MB of Flash memory, connected to the processor using
the Local Bus interface. The Flash uses 16-bit wide Spansion SG29GL family devices,
arranged in 128 KB sectors. The Flash has an erase capacity of 100,000 cycles per
sector and typical data retention of 20 years.
The Flash supports page-mode accesses, which allows the Flash array to be accessed
in 256 MB pages for maximum bus bandwidth.
CAUTION
If a hard reset occurs during a Flash write cycle, integrity of Flash data cannot be guaranteed.
Table 4-5 Flash Details
Size
Banks Flash Bank Organization
512 MB
2
2 x 2 Gbit (S70 stacked die)
