Publication No. PPC11A-HRM/1
Specifications 133
B •
Statement of Volatility
B.1 Volatile Memory
The PPC11A contains volatile memory, i.e. memory in which the contents are lost
when power is removed. None of this volatile memory is capable of write protection.
Table B-1 Volatile Memory
Memory Type
Size
User
Modifiable?
User Access
to Data?
Function
Process to Clear
DDR3L SDRAM
4 or 8 GB
Yes
Yes
Main memory Remove power
SRAM
1536 bytes
Yes
No
BMM SRAM
Remove power
T1042 L2 Cache
a
256 KB per core Yes
No
NXP SoC
Remove power
T1042 L3 CPC
a
256 KB
Yes
No
NXP SoC
Remove power
T2081 L2 Cache
a
2 MB
Yes
No
NXP SoC
Remove power
T2081 CPC
a
512 KB
Yes
No
NXP SoC
Remove power
a.
T1042 or T2081 processor is fitted – not both.
B.2 Non-Volatile Memory
The PPC11A contains non-volatile memory, i.e. memory in which the contents are
retained when power is removed.
Table B-2 Non-Volatile Memory
Memory Type
Size
User
Modifiable?
User Access
to Data?
Write
Protectable?
Function
Process to Clear
Flash (on-chip)
N/A
No
No
N/A
Master FPGA
configuration data
Erase via JTAG interface
on TAC
Flash (on-chip)
N/A
No
No
N/A
Slave FPGA
configuration data
Erase via JTAG interface
on TAC
Flash (SPI)
64 Mbit
TBD
TBD
No
TBD
Not user-erasable
Flash (Recovery SPI)
4 MB
No
No
Yes
U-Boot recovery data
Not user-erasable
nvSRAM
4 Mbit
Yes
Yes
Yes
Boot parameters,
environment variables
and user memory
Execute software erase routine
Flash (NOR)
512 MB
Yes
Yes
Yes
Boot code, user memory,
BIT results,
MAC/configuration data
Execute software erase routine
EEPROM (I
2
C)
256 Kbit
Yes
Yes
Yes
Alternate RCW/
user memory
Execute software erase routine
Flash
32 KB
Yes
No
No
BMM firmware
Execute software erase routine
EEPROM
256 Bytes Yes
Yes
No
BMM FRU/
configuration data
Execute software erase routine
(continued overleaf)
