Triggering
3
2
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
App
Index
6-45
IM 701310-01E
Bit Rate
If the clock is set to OFF, the DL9000 samples the data source at the specified bit rate.
Selectable range: 1 kbps to 50 Mbps in 1-kbps steps
CS
If the clock is set to ON, the period that the DL9000 tests the data source can be
controlled using the CS state condition.
ON
Tests the data source while the state condition is met.
OFF Tests the data source at all times.
• State Condition
Set each signal state to H, L, or X. The state condition is true when the selected state
and the input signal state meet the following condition.
H
When the signals are high
L
When the signals are low
X
Not used as a trigger condition (Don’t care)
* The level for determining high or low is the trigger level that you set below when you set the
signal to a channel from CH1 to CH4.
• Logic
You can select the state condition logic. The state condition is true when the logic
condition is met.
AND
When the state of all signals matches
OR
When the state of any signal matches
Latch
If the clock is set to ON, you can specify the timing when the sampled data source
pattern is compared with the specified pattern. If the source is set to X, comparison is
made on each clock.
You can select the latch source edge that specifies when the data patterns are compared.
On the rising edge
On the falling edge
Trigger Level
When the data, clock, CS, or latch source is set to CH1 to CH4, you can set the trigger
level for each source.
• The selectable range is 8 divisions within the screen. The resolution is 0.01 divisions.
For example, if the T/div setting is 2 mV/division, the resolution is 0.02 mV.
• You can reset the trigger level to the current offset voltage by pressing RESET.
Hysteresis
See section 6.5 for details.
Example
Clock
Data
CS
Latch
1
2
3
4
5
6
7
8
9
10
Data detection
The latch signal specifies the time when data is compared.
Trigger point
6.14 Triggering on a Serial Pattern Signal
