16-44
IM 765501-01E
16.3 Status Reports
Operation of the Status Byte
A service request is issued when bit 6 of the status
byte becomes 1. Bit 6 is set to 1 when any of the other
bits becomes a 1 (when the corresponding bit of the
service request enable register is also set to 1).
For example, if an event takes place and the logical
OR of each bit of the standard event register and the
corresponding bit in the enable register is 1, bit 5
(ESB) will be set to 1. In this case, if bit 5 of the
service request enable register is 1, bit 6 (MSS) will be
set to 1, thus requesting service from the controller.
It is also possible to check what type of event has
occurred by reading the contents of the status byte.
Reading from the Status Byte
The following two methods are provided for reading the
status byte.
Inquiry Using the *STB? Query
Making an inquiry using the
*STB?
query sets bit 6 to
MSS. This causes the MSS to be read. After
completion of the read-out, none of the bits in the
status byte will be cleared.
Serial Polling
Execution of a serial polling changes bit 6 to RQS.
This causes RQS to be read. After completion of the
read-out, only RQS is cleared. It is not possible to
read MSS using serial polling.
Clearing the Status Byte
No method is provided for forcibly clearing all the bits
in the status byte. The bits that are cleared for each
operation are shown below.
When a Query Is Made Using the *STB? Command
No bits are cleared.
When a Serial Polling Is Executed
Only the RQS bit is cleared.
When a *CLS Command Is Received
When the *CLS command is received, the status byte
itself is not cleared, but the contents of the standard
event register (which affects the bits in the status byte)
are cleared. As a result, the corresponding bits in the
status byte are cleared, except bit 4 (MAV), since the
output queue cannot be emptied by the *CLS
command. However, the output queue will also be
cleared if the *CLS command is received just after a
program message terminator.
16.3.3 Standard Event Register
Standard Event Register
URQ
6
PON
7
5
4
3
2
1
0
CME EXE DDE QYERQCOPC
Bit 7 PON (Power ON)
Set to 1 when the power is turned ON.
Bit 6 URQ (User Request)
Not used (always 0)
Bit 5 CME (Command Error)
Set to 1 when the command syntax is incorrect.
Example Incorrectly spelled command name; 9
used in octal data.
Bit 4 EXE (Execution Error)
Set to 1 when the command syntax is correct but the
command cannot be executed in the current state.
Example Parameters are outside the range.
Bit 3 DDE (Device Error)
Set to 1 when execution of the command is not
possible due to an internal problem in the instrument
that is not a command error or an execution error.
Bit 2 QYE (Query Error)
Set to 1 if the output queue is empty or if the data is
missing even after a query has been sent.
Example No response data; data is lost due to an
overflow in the output queue.
Bit 1 RQC (Request Control)
Not used (always 0)
Bit 0 OPC (Operation Complete)
Set to 1 when the operation designated by the *OPC
command (see section 16.2.13) has been completed.
Bit Masking
To mask a bit in the standard event register so that it
does not cause bit 5 (ESB) of the status byte to
change, set the corresponding bit in the standard event
enable register to 0.
For example, to mask bit 2 (QYE) so that ESB will not
be set to 1, even if a query error occurs, set bit 2 of the
standard event enable register to 0. This can be done
using the *ESE command. To inquire whether each bit
of the standard event enable register is 1 or 0, use the
*ESE?. For details on the *ESE command, see
section 16.2.13.
