16-43
IM 765501-01E
Communication
Commands
3
2
1
6
5
4
9
8
7
12
11
10
15
14
13
18
17
16
16
Index
App
Registers and Queues That Affect the
Status Byte
Registers that affect the bits of the status byte are
shown below.
• Standard event register: Sets bit 5 (ESB) of the status byte to 1
or 0.
• Output queue:
Sets bit 4 (MAV) of the status byte to 1
or 0.
• Source event register:
Sets bit 1 (SSB) of the status byte to 1
or 0.
• Measure event register: Sets bit 0 (MSB) of the status byte to 1
or 0.
• Error queue:
Sets bit 2 (EAV) of the status byte to 1
or 0.
Enable Registers
Registers that are used to mask a bit so that the bit will
not affect the status byte even when it is set to 1, are
shown below.
• Status byte:
Mask the bits using the service
request enable register.
• Standard event register: Mask the bits using the standard event
enable register.
• Source event register:
Mask the bits using the source event
enable register.
• Measure event register: Mask the bits using the measure event
enable register.
Writing/Reading from Registers
The *ESE command is used to set the bits in the
standard event enable register to 1’s or 0’s. The
*ESE? command is used to query whether the bits in
the standard event enable register are 1’s or 0’s. For
details regarding these commands, see section
16.2.13.
16.3.2 Status Byte
Status Byte
7
6 ESB MAV 3 EAV SSB MSB
RQS
MSS
Bits 3 and 7
Not used (always 0)
Bit 0 MSB (Measure Event Summary Bit)
Set to 1 when the logical product of each bit of the
measure event register and each bit of the
corresponding enable register is 1. See the page 16-
47.
Bit 1 SSB (Source Event Summary Bit)
Set to 1 when the logical product of each bit of the
source event register and each bit of the
corresponding enable register is 1. See the page 16-
46.
Bit 2 EAV (Error Available)
Set to 1 when the error queue is not empty. In other
words, this bit is set to 1 when an error occurs. See
the page 16-48.
Bit 4 MAV (Message Available)
Set to 1 when the output queue is not empty. In other
words, this bit is set to 1 when there is data to be
transmitted. See the page 16-48.
Bit 5 ESB (Event Summary Bit)
Set to 1 when the logical product of each bit of the
standard event register and each bit of the
corresponding enable register is 1. See the page 16-
44.
Bit 6 RQS (Request Service)/MSS (Master Status
Summary)
Set to 1 when the logical AND of the status byte
excluding bit 6 and the service request enable register
is not 0. In other words, this bit is set to 1 when the
instrument is requesting service from the controller.
RQS is set to 1 when the MSS bit changes from 0 to 1,
and cleared when serial polling is carried out or when
the MSS bit changes to 0.
Bit Masking
To mask a bit in the status byte so that it does not
cause an SRQ, set the corresponding bit of the service
request enable register to 0.
For example, to mask bit 2 (EAV) so that service is not
requested when an error occurs, set bit 2 of the service
request enable register to 0. This can be done using
the *SRE command. To query whether each bit of the
service request enable register is 1 or 0, use *SRE?.
For details on the *SRE command, see section
16.2.13.
16.3 Status Reports
