Communication
Commands
10-37
IM 755601-01E
10
Summary of the Registers and Queues
Name
Function
Write
Read
Status byte
—
Serial polling
(RQS),
*STB?
(MSS)
Service request Status byte mask
*SRE
*SRE?
enable register
Standard event Changes in device
—
*ESR?
register
status
Standard event Standard event
*ESE
*ESE?
enable register register mask
Extended event Changes in device
—
STATus:EESR?
register
status
Extended event Extended event
STATus:EESE
STATus:EESE?
enable register register mask
Status register Current device status —
STATus:CONDition?
Transition filter Conditions that
STATus:FILTer<x> STATus:FILTer<x>?
change the extended
event register
Output queue Stores a response All query commands
message to a query
Error queue
Stores the error No. —
STATus:ERRor?
and message
Registers and Queues that Affect the Status Byte
Registers that affect the contents of the status byte are
shown below.
Standard event register: Sets bit 5 (ESB) of the status byte to “1” or “0.”
Output queue:
Sets bit 4 (MAV) of the status byte to “1” or “0.”
Extended event register: Sets bit 3 (EES) of the status byte to “1” or “0.”
Error queue:
Sets bit 2 (EAV) of the status byte to “1” or “0.”
Enable Registers
Registers that are used to mask a bit so that the bit will
not affect the status byte, even if it is set to 1, are
shown below.
Status byte:
Mask the bits using the service request enable register.
Standard event register: Mask the bits using the standard event enable register.
Extended event register: Mask the bits using the extended event enable register.
Reading and Writing to the Registers
For example, the
*ESE
command is used to set the bits
in the standard event enable register to 1’s or 0’s. The
*ESE?
command is used to query whether the bits in the
standard event enable register are 1’s or 0’s. For
details regarding these commands, see section 10.2.
10.3.2
Status Byte
Status byte
7
6 ESBMAVEES EAV 1
0
RQS
MSS
Bits 0, 1, and 7
Not used (always 0)
Bit 2 EAV (Error Available)
Set to “1” when the error queue is not empty. In other
words, this bit is set to “1” when an error occurs. See
page 10-40.
Bit 3 EES (Extend Event Summary Bit)
Set to “1” when the logical product of the extended
event register and the corresponding event register is
not “0.” In other words, this bit is set to “1” when an
event occurs inside the instrument. See page 10-39.
Bit 4 MAV (Message Available)
Set to “1” when the output queue is not empty. In
other words, this bit is set to “1” when there are data to
be transmitted. See page 10-40.
Bit 5 ESB (Event Summary Bit)
Set to “1” when the logical product of the standard
event register and the corresponding event register is
not “0.” In other words, this bit is set to “1” when an
event occurs inside the instrument. See page 10-39.
Bit 6 RQS (Request Service)/MSS (Master Status
Summary)
Set to “1” when the logical AND of the status byte
excluding Bit 6 and the service request enable register
is not “0.” In other words, this bit is set to “1” when the
instrument is requesting service from the controller.
RQS is set to “1” when the MSS bit changes from “0”
to “1,” and cleared when the MSS bit changes to “0.”
Bit Masking
If you wish to mask a certain bit of the status byte so
that it does not cause a SRQ, set the corresponding bit
of the service request enable register to “0.”
For example, to mask bit 2 (EAV) so that service is not
requested when an error occurs, set bit 2 of the service
request enable register to “0.” This is done using the
*SRE
command. The
*SRE?
request command can be
used to query the service request enable register to
check whether each bit is set to “1” or “0.” For details
regarding the
*SRE
command, see section 10.2.
10.3 Status Report
