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60 www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2: MicroBlaze Architecture
TLB Access
When the MMU translates a virtual address (the combination of PID and effective address) into a
physical address, it first examines the appropriate shadow TLB for the page translation entry. If an
entry is found, it is used to access physical memory. If an entry is not found, the MMU examines the
UTLB for the entry. A delay occurs each time the UTLB must be accessed due to a shadow TLB
miss. The miss latency ranges from 2-32 cycles. The DTLB has priority over the ITLB if both
simultaneously access the UTLB.
Figure 2-21, page 62 shows the logical process the MMU follows when examining a page-
translation entry in one of the shadow TLBs or the UTLB. All valid entries in the TLB are checked.
A TLB hit occurs when all of the following conditions are met by a TLB entry:
•
The entry is valid
•
The TAG field in the entry matches the effective address EPN under the control of the SIZE
field in the entry
•
The TID field in the entry matches the PID
If any of the above conditions are not met, a TLB miss occurs. A TLB miss causes an exception,
described as follows:
A TID value of 0x00 causes the MMU to ignore the comparison between the TID and PID. Only the
TAG and EA[EPN] are compared. A TLB entry with TID=0x00 represents a process-independent
translation. Pages that are accessed globally by all processes should be assigned a TID value of
0x00. A PID value of 0x00 does not identify a process that can access any page. When PID=0x00,
a page-translation hit only occurs when TID=0x00. It is possible for software to load the TLB with
multiple entries that match an EA[EPN] and PID combination. However, this is considered a
programming error and results in undefined behavior.
When a hit occurs, the MMU reads the RPN field from the corresponding TLB entry. Some or all of
the bits in this field are used, depending on the value of the SIZE field (see
Table 2-37 ). For
example, if the
SIZE
field specifies a 256 kB page size, RPN[0:13] represents the physical page
number and is used to form the physical address. RPN[14:21] is not used, and software must clear
those bits to 0 when initializing the TLB entry. The remainder of the physical address is taken from
the page-offset portion of the EA. If the page size is 256 kB, the 32-bit physical address is formed by
concatenating RPN[0:13] with bits14:31 of the effective address.
Prior to accessing physical memory, the MMU examines the TLB-entry access-control fields. These
fields indicate whether the currently executing program is allowed to perform the requested memory
access.
If access is allowed, the MMU checks the storage-attribute fields to determine how to access the
page. The storage-attribute fields specify the caching policy for memory accesses.
TLB Access Failures
A TLB-access failure causes an exception to occur. This interrupts execution of the instruction that
caused the failure and transfers control to an interrupt handler to resolve the failure. A TLB access
can fail for two reasons:
•
A matching TLB entry was not found, resulting in a TLB miss
•
A matching TLB entry was found, but access to the page was prevented by either the storage
attributes or zone protection
When an interrupt occurs, the processor enters real mode by clearing MSR[VM] to 0. In real mode,
all address translation and memory-protection checks performed by the MMU are disabled. After
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