MicroBlaze Processor Reference Guide
33
UG081 (v14.7)
Registers
Branch Target Register (BTR)
The Branch Target Register only exists if the MicroBlaze processor is configured to use exceptions.
The register stores the branch target address for all delay slot branch instructions executed while
MSR[EIP] = 0. If an exception is caused by an instruction in a delay slot (that is, ESR[DS]=1), the
exception handler should return execution to the address stored in BTR instead of the normal
exception return address stored in R17. When read with the MFS instruction, the BTR is specified
by setting Sa = 0x000B. The BTR register is illustrated in
provides bit
descriptions and reset values.
Instruction
storage
20
DIZ
Instruction storage - Zone protection
0 = Did not occur
1 = Occurred
0
21:26
Reserved
0
Data TLB
miss
20
Reserved
0
21
S
Data TLB miss - Store instruction
0 = Did not occur
1 = Occurred
0
22:26
Reserved
0
Instruction
TLB miss
20:26
Reserved
0
Table 2-12:
Exception Specific Status (ESS)
(Continued)
Exception
Cause
Bits
Name
Description
Reset Value
0
31
↑
BTR
Figure 2-7:
BTR
Table 2-13:
Branch Target Register (BTR)
Bits
Name
Description
Reset Value
0:31
BTR
Branch target address used by handler when
returning from an exception caused by an
instruction in a delay slot.
Read-only
0x00000000
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