242
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 5:
MicroBlaze Instruction Set Architecture
sbi
Store Byte Immediate
Description
Stores the contents of the least significant byte of register rD, into the memory location that results
from adding the contents of register rA and the value IMM, sign-extended to 32 bits.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-
access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.
Pseudocode
Addr
←
(rA)
+
sext(IMM)
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC]
←
10010;ESR[S]
←
1
MSR[UMS]
←
MSR[UM]; MSR[VMS]
←
MSR[VM]; MSR[UM]
←
0; MSR[VM]
←
0
else if Access_Protected(Addr) and MSR[VM] = 1 then
ESR[EC]
←
10000;ESR[S]
←
1; ESR[DIZ]
←
No-access-allowed
MSR[UMS]
←
MSR[UM]; MSR[VMS]
←
MSR[VM]; MSR[UM]
←
0; MSR[VM]
←
0
else
Mem(Addr)
← (
rD)[24:31]
Registers Altered
•
MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if an exception is generated
•
ESR[EC], ESR[S], if an exception is generated
•
ESR[DIZ], if a data storage exception is generated
Latency
•
1 cycle with
C_AREA_OPTIMIZED=0
•
2 cycles with
C_AREA_OPTIMIZED=1
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to
use as the immediate operand. This behavior can be overridden by preceding the Type B instruction
with an imm instruction. See the instruction
for details on using 32-bit immediate
values.
sbi
rD, rA, IMM
1 1 1 1 0 0
rD
rA
IMM
0
6
11
16
31
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