250
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 5:
MicroBlaze Instruction Set Architecture
sw
Store Word
Description
Stores the contents of register rD, into the word aligned memory location that results from adding
the contents of registers rA and rB.
If the R bit is set, the bytes in the stored word are reversed , storing data with the opposite endianness
of the endianness defined by
C_ENDIANNESS
and the E bit (if virtual protected mode is enabled).
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-
access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.
An unaligned data access exception occurs if the two least significant bits in the address are not zero.
Pseudocode
Addr
←
(rA) + (rB)
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC]
←
10010;ESR[S]
←
1
MSR[UMS]
←
MSR[UM]; MSR[VMS]
←
MSR[VM]; MSR[UM]
←
0; MSR[VM]
←
0
else if Access_Protected(Addr) and MSR[VM] = 1 then
ESR[EC]
←
10000;ESR[S]
←
1; ESR[DIZ]
←
No-access-allowed
MSR[UMS]
←
MSR[UM]; MSR[VMS]
←
MSR[VM]; MSR[UM]
←
0; MSR[VM]
←
0
else if Addr[30:31]
≠
0 then
ESR[EC]
←
00001; ESR[W]
←
1; ESR[S]
←
1; ESR[Rx]
←
rD
else
Mem(Addr)
← (
rD)[0:31]
Registers Altered
•
MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage
exception is generated
•
ESR[EC], ESR[S], if an exception is generated
•
ESR[DIZ], if a data storage exception is generated
•
ESR[W], ESR[Rx], if an unaligned data access exception is generated
Latency
•
1 cycle with
C_AREA_OPTIMIZED=0
•
2 cycles with
C_AREA_OPTIMIZED=1
Note
The word reversed instruction is only valid if MicroBlaze is configured to use reorder instructions
(
C_USE_REORDER_INSTR = 1
).
sw
rD, rA, rB
swr
rD, rA, rB
1 1 0 1 1 0
rD
rA
rB
0 R 0 0 0 0 0 0 0 0 0
0
6
11
16
21
31
Содержание MicroBlaze
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