200
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 5:
MicroBlaze Instruction Set Architecture
Pseudocode
if MSR[UM] = 1 then
ESR[EC]
←
00111
else
x
←
FSLx
if x >= C_FSL_LINKS then
x
←
0
(rD)
←
FSLx_S_DATA | Sx_AXIS_TDATA
if (n = 1) then
MSR[Carry]
←
(FSLx_S_EXISTS | Sx_AXIS_TVALID)
if (FSLx_S_CONTROL | Sx_AXIS_TLAST
≠
c) and
(FSLx_S_EXISTS | Sx_AXIS_TVALID) then
MSR[FSL]
←
1
if (e = 1) then
ESR[EC]
←
00000
ESR[ESS]
←
instruction bits [28:31]
EDR
←
FSLx_S_DATA | Sx_AXIS_TDATA
Registers Altered
•
rD, unless an exception is generated, in which case the register is unchanged
•
MSR[FSL]
•
MSR[Carry]
•
ESR[EC], in case a stream exception or a privileged instruction exception is generated
•
ESR[ESS], in case a stream exception is generated
•
EDR, in case a stream exception is generated
Latency
•
1 cycle with
C_AREA_OPTIMIZED=0
•
2 cycles with
C_AREA_OPTIMIZED=1
The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction
can be completed. Interrupts are served when the parameter
C_USE_EXTENDED_FSL_INSTR
is
set to 1, and the instruction is not atomic.
Note
To refer to an FSLx interface in assembly language, use rfsl0, rfsl1, ... rfsl15.
The blocking versions of this instruction should not be placed in a delay slot when the parameter
C_USE_EXTENDED_FSL_INSTR
is set to 1, since this prevents interrupts from being served.
For non-blocking versions, an rsubc instruction can be used to decrement an index variable.
The ‘e’ bit does not have any effect unless
C_FSL_EXCEPTION
is set to 1.
These instructions are only available when the MicroBlaze parameter
C_FSL_LINKS
is greater
than 0.
The extended instructions (exception, test and atomic versions) are only available when the
MicroBlaze parameter
C_USE_EXTENDED_FSL_INSTR
is set to 1.
It is not recommended to allow these instructions in user mode, unless absolutely necessary for
performance reasons, since that removes all hardware protection preventing incorrect use of a link.
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