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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2:
MicroBlaze Architecture
Self-modifying Code
When using self-modifying code software must ensure that the modified instructions have been
written to memory prior to fetching them for execution. There are several aspects to consider:
•
The instructions to be modified may already have been fetched prior to modification:
♦
into the instruction prefetch buffer,
♦
into the instruction cache, if it is enabled,
♦
into a stream buffer, if instruction cache stream buffers are used,
♦
into the instruction cache, and then saved in a victim buffer, if victim buffers are used.
To ensure that the modified code is always executed instead of the old unmodified code,
software must handle all these cases.
•
If one or more of the instructions to be modified is a branch, and the branch target cache is
used, the branch target address may have been cached.
To avoid using the cached branch target address, software must ensure that the branch target
cache is cleared prior to executing the modified code.
•
The modified instructions may not have been written to memory prior to execution:
♦
they may be en route to memory, in temporary storage in the interconnect or the memory
controller,
♦
they may be stored in the data cache, if write-back cache is used,
♦
they may be saved in a victim buffer, if write-back cache and victim buffers are used.
Software must ensure that the modified instructions have been written to memory before being
fetched by the processor.
The annotated code below shows how each of the above issues can be addressed. This code assumes
that both instruction cache and write-back data cache is used. If not, the corresponding instructions
can be omitted.
The following code exemplifies storing a modified instruction, when using AXI interconnect:
swi
r5,r6,0
; r5 = new instruction
; r6 = physical instruction address
wdc.flush r6,r0
; flush write-back data cache line
mbar
1
; ensure new instruction is written to memory
wic
r7,r0
; invalidate line, empty stream & victim buffers
; r7 = virtual instruction address
mbar
2
; empty prefetch buffer, clear branch target cache
The following code exemplifies storing a modified instruction, when using XCL:
swi
r5,r6,0
; r5 = new instruction
; r6 = physical instruction address
wdc.flush r6,r0
; flush write-back data cache line
lwi
r0,r6,0
; read back new instruction from memory to ensure it
; has been written to memory
wic
r7,r0
; invalidate line, empty stream & victim buffers
; r7 = virtual instruction address
mbar
2
; empty prefetch buffer, clear branch target cache
The physical and virtual addresses above are identical, unless MMU virtual mode is used. If the
MMU is enabled, the code sequences must be executed in real mode, since WIC and WDC are
privileged instructions.
The first instruction after the code sequences above must not be modified, since it may have been
prefetched.
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