MicroBlaze Processor Reference Guide
257
UG081 (v14.7)
Instructions
if F = 1 and cacheline.Dirty then
for i
=
0 .. C_DCACHE_LINE_LEN - 1 loop
if cacheline.Valid[i] then
Mem(cachelin i * 4)
←
cacheline.Data[i]
if T = 0 then
cacheline.Tag
←
0
else if cacheline.Address = cacheline_addr then
cacheline.Tag
←
0
if E = 1 then
if F = 1 then
request external cache flush with address
else
request external cache invalidate with address
Registers Altered
•
ESR[EC], in case a privileged instruction exception is generated
Latency
•
2 cycles for wdc.clear
•
2 cycles for wdc with
C_AREA_OPTIMIZED=1
•
3 cycles for wdc with
C_AREA_OPTIMIZED=0
•
2 + N cycles for wdc.flush, where N is the number of clock cycles required to flush the cache
line to memory when necessary
Note
The
wdc
,
wdc.flush
and
wdc.clear
instructions are independent of data cache enable (MSR[DCE]),
and can be used either with the data cache enabled or disabled.
The
wdc.clear
instruction is intended to invalidate a specific area in memory, for example a buffer
to be written by a Direct Memory Access device. Using this instruction ensures that other cache
lines are not inadvertently invalidated, erroneously discarding data that has not yet been written to
memory.
The address of the affected cache line is always the physical address, independent of the parameter
C_USE_MMU
and whether the MMU is in virtual mode or real mode.
When using
wdc.flush
in a loop to flush the entire cache, the loop can be optimized by using Ra as
the cache base address and Rb as the loop counter:
addik
r5,r0,C_DCACHE_BASEADDR
addik
r6,r0,C_DCACHE_BYTE_SIZE-C_DCACHE_LINE_LEN*4
loop:
wdc.flush r5,r6
bgtid
r6,loop
addik
r6,r6,-C_DCACHE_LINE_LEN*4
When using
wdc.clear
in a loop to invalidate a memory area in the cache, the loop can be optimized
by using Ra as the memory area base address and Rb as the loop counter:
addik
r5,r0,memory_area_base_address
addik
r6,r0,memory_area_byte_size-C_DCACHE_LINE_LEN*4
loop:
wdc.clear r5,r6
bgtid
r6,loop
addik
r6,r6,-C_DCACHE_LINE_LEN*4
Содержание MicroBlaze
Страница 1: ...MicroBlaze Processor Reference Guide Embedded Development Kit EDK 14 7 UG081 v14 7...
Страница 4: ...MicroBlaze Processor Reference Guide www xilinx com UG081 v14 7...
Страница 8: ...8 www xilinx com MicroBlaze Processor Reference Guide UG081 v14 7 Chapter 1 Introduction Send Feedback...
Страница 262: ...262 www xilinx com MicroBlaze Processor Reference Guide UG081 v14 7 Send Feedback...