MicroBlaze Processor Reference Guide
185
UG081 (v14.7)
Instructions
brki
Break Immediate
Description
Branch and link to the instruction located at address value in IMM, sign-extended to 32 bits. The
current value of PC will be stored in rD. The BIP flag in the MSR will be set, and the reservation bit
will be cleared.
When MicroBlaze is configured to use an MMU (
C_USE_MMU
>= 1) this instruction is privileged,
except as a special case when “
brki
rD,
C_BASE_0x8
” or “
brki
rD,
C_BASE_0x18
” is used to perform a Software Break. This means that, apart from the
special case, if the instruction is attempted in User Mode
(MSR[UM]
= 1) a Privileged Instruction
exception occurs.
As a special case, when MicroBlaze is configured to use an MMU (
C_USE_MMU
>= 1) and “
brki
rD,
C_BASE_0x8
” or “
brki
rD,
C_BASE_0x18
” is used to perform a
Software Break, the Machine Status Register bits User Mode and Virtual Mode are cleared.
Pseudocode
if MSR[UM] and IMM
≠
C_BASE_0x8 and IMM
≠
C_BASE_0x18 then
ESR[EC]
←
00111
else
(rD)
←
PC
PC
←
sext(IMM)
MSR[BIP]
← 1
Reservation
← 0
if IMM = C_BASE_0x8 or IMM = C_BASE_0x18 then
MSR[UMS]
←
MSR[UM]MSR[UM]
←
0
MSR[VMS]
←
MSR[VM]MSR[VM]
←
0
Registers Altered
•
rD, unless an exception is generated, in which case the register is unchanged
•
PC
•
MSR[BIP], MSR[UM], MSR[VM]
•
ESR[EC], in case a privileged instruction exception is generated
Latency
•
3 cycles
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to
use as the immediate operand. This behavior can be overridden by preceding the Type B instruction
with an imm instruction. See the instruction
for details on using 32-bit immediate
values.
As a special case, the imm instruction does not override a Software Break “
brki
rD,
0x18
” when
C_USE_DEBUG
. is set, irrespective of the value of
C_BASE_VECTORS,
to allow Software Break
after an imm instruction.
brki
rD, IMM
1 0 1 1 1 0
rD
0 1 1 0 0
IMM
0
6
11
16
31
Содержание MicroBlaze
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