100
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 3:
MicroBlaze Signal Interface Description
M_AXI_DC_BID
M_AXI_DC
I
Slave Response ID
M_AXI_DC_BVALID
M_AXI_DC
I
Slave Write response valid
M_AXI_DC_BREADY
M_AXI_DC
O
Master Response ready
M_AXI_DC_BUSER
M_AXI_DC
I
Slave Write response user signals
M_AXI_DC_WACK
M_ACE_DC
O
Slave Write acknowledge
M_AXI_DC_ARID
M_AXI_DC
O
Master Read address ID
M_AXI_DC_ARADDR
M_AXI_DC
O
Master Read address
M_AXI_DC_ARLEN
M_AXI_DC
O
Master Burst length
M_AXI_DC_ARSIZE
M_AXI_DC
O
Master Burst size
M_AXI_DC_ARBURST
M_AXI_DC
O
Master Burst type
M_AXI_DC_ARLOCK
M_AXI_DC
O
Master Lock type
M_AXI_DC_ARCACHE
M_AXI_DC
O
Master Cache type
M_AXI_DC_ARPROT
M_AXI_DC
O
Master Protection type
M_AXI_DC_ARQOS
M_AXI_DC
O
Master Quality of Service
M_AXI_DC_ARVALID
M_AXI_DC
O
Master Read address valid
M_AXI_DC_ARREADY
M_AXI_DC
I
Slave Read address ready
M_AXI_DC_ARUSER
M_AXI_DC
O
Master Read address user signals
M_AXI_DC_ARDOMAIN
M_ACE_DC
O
Master Read address domain
M_AXI_DC_ARSNOOP
M_ACE_DC
O
Master Read address snoop
M_AXI_DC_ARBAR
M_ACE_DC
O
Master Read address barrier
M_AXI_DC_RID
M_AXI_DC
I
Slave Read ID tag
M_AXI_DC_RDATA
M_AXI_DC
I
Slave Read data
M_AXI_DC_RRESP
M_AXI_DC
I
Slave Read response
M_AXI_DC_RLAST
M_AXI_DC
I
Slave Read last
M_AXI_DC_RVALID
M_AXI_DC
I
Slave Read valid
M_AXI_DC_RREADY
M_AXI_DC
O
Master Read ready
M_AXI_DC_RUSER
M_AXI_DC
I
Slave Read user signals
M_AXI_DC_RACK
M_ACE_DC
O
Master Read acknowledge
M_AXI_DC_ACVALID
M_ACE_DC
I
Slave Snoop address valid
M_AXI_DC_ACADDR
M_ACE_DC
I
Slave Snoop address
M_AXI_DC_ACSNOOP
M_ACE_DC
I
Slave Snoop address snoop
M_AXI_DC_ACPROT
M_ACE_DC
I
Slave Snoop address protection type
Table 3-1:
Summary of MicroBlaze Core I/O
(Continued)
Signal
Interface
I/O
Description
Содержание MicroBlaze
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