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VM1548C Theory Of Operation
99
D
ATA
L
OAD
Loading of data into the I/O Word Buffer occurs when the VMIP receives the SCPI command for
writing data. The Timing and Control FPGA decodes the address and control bits from the VMIP
bus and generates the DOE* signal to the Read/Write Data Buffer. The Timing and Control FPGA
then issues the WRITE0* signal to the selected I/O Word Buffer, thus latching the data. The I/O
buffers are enabled and configured to transmit data from channel 0 to the UUT upon receipt of the
proper clock or trigger.
VMIP
Bus
Timing
and
Control
Direction
Control
I/O
Data
Buffer
I/O
Word
Buffer
Port
Decoder
OR
Read /
Write
Data
Buffer
Read
Clock
Enable
33K
100K
VCC
200K
I/O from
front panel
WRITE0
OUTENA0
WRITE0
Data Bus
Output to
Front Panel
Data Bus
Control Lines
WRITE*
DOE*
D8-D15
Address 0,1,2
Data Bus
PORT1*
D8-D15
PORT2*
PORTENA*
CLKOUTENA0
IN*/OUT0
F
IGURE
5-1:
W
RITE
M
ODE
B
UFFER
C
ONFIGURATION
Содержание VM1548C
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Страница 5: ...www vxitech com VM1548C Preface 5 Clock Enable 102 Latch Data 103 Read Data 104 INDEX 105...
Страница 16: ...VXI Technology Inc 16 VM1548C Introduction...
Страница 44: ...VXI Technology Inc 44 VM1548C Programming...
Страница 96: ...VXI Technology Inc 96 VM1548C Command Dictionary...