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VM1548C Programming
35
OUTP:CLOC:ENAB <port> ON
commands inform the timing and control circuitry that the
front panel clock lines are used as outputs. This allows the VM1548C to furnish the clock source.
OUTP:CLOC:SOUR <port> IMM
commands inform the timing and control circuitry to drive
the front panel clock lines using the immediate (word serial event) trigger.
The
OUTP:REG:SOUR <port> IMM
commands select the immediate (word serial event) clock
as the trigger method for the selected ports to output data to the UUT (VM1548C through wrap-
around cable). When these commands are received, the VM1548C timing and control circuitry
will generate the PORTENA* signal to the port decoder. The port decoder then clocks the write
clock enable latch selecting the CLKOUTENA. The CLKOUTENA signals are applied to the I/O
data and word buffers enabling the output clock line.
The
SOUR:DATA:ENAB <port> ON
enables the selected ports for a write, in this case ports 0,
1, and 2. The
SOUR:DATA:ENAB <port> OFF
enables the selected ports to read, in this case
ports 3, 4, and 5. The
SOUR:DATA <port> <data>
commands writes the data into the specified
ports as previously described.
The
STAT:INT:ENAB EXT 5
and
STAT:INT:PTR ON
commands enable the interrupt to
occur when the CLK 5 signal is received and sets the polarity of this interrupt to the positive edge.
TRIG:SEQ:IMM
command will generate a short pulse that will initiate the transfer of data from
ports 0, 1, and 2 to ports 3, 4, and 5. When CLK 5 has been received, the VM1548C module sends
an Interrupt Request (IRQ*) informing the slot 0 controller via the VMIP that the transfer has
occurred. The
READ? <port>
will then fetch the data from the specified ports.
Содержание VM1548C
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