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Hardware Configuration

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SLWU086C – November 2013 – Revised January 2016

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TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide

2.3

LEDs

2.3.1

Power and Configuration LEDs

Several LEDs are on the TSW14J56 EVM to indicate the presence of power and the state of the FPGA.
The description of these LEDs can be found in

Table 3

.

Table 3. Power and Configuration LED Description of the TSW14J56 Device

Component

Description

D17

On if DDR3 VREF power is good

D10

On if 5V board power is present

D32

On if power monitor device indicates that a power net is out of tolerance

D11

On if +1.0 V is within specification

D13

On if VCCD_1.5 V is within specification

D16

On if VCC_1.5 V is within specification

D21

On if VCC_2.5 V is within specification

D23

On if VCCA_GXB_3.0 V is within specification

D25

On if VCC_PLL_2.5 V is within specification

D26

On if VCC_0.85V is within specification

D27

On if VCCDDR_1.5 V is within specification

D30

On if VTTDDR_0.75 V is within specification

D34

On if VAR power is present

D33

On if USB_1.2 V is within specification

D28

On after FPGA completes configuration

2.3.2

Status LEDs

Eight status LEDs on the TSW14J56EVM indicate the status of the FPGA, DDR3, and JESD204B
interface:

D1

– Indicates DAC EVM established SYNC with the TSW14J56 device when off

D2

– Indicates presence of device clock from DAC EVM when blinking

D3

– Indicates ADC EVM established SYNC with the TSW14J56 device when off

D4

– Indicates presence of device clock from ADC EVM when blinking

D5

– Not used

D6

– DDR3 initialization and calibration complete when off

D7

– DDR3 ready when off

D8

– DDR3 pass calibration and initialization if on

2.3.3

Connectors

2.3.3.1

SMA Connectors

The TSW14J56 has 9 SMA connectors. The connectors are defined below:

J6

GBTCLK0N

Spare Transceiver reference clock negative input

J5

GBTCLK0P

Spare Transceiver reference clock positive input

J13

TRIG_IN

Adjustable level CMOS trigger input. Default level is 1.8 V

J7

TRIG_OUT_A

Adjustable level CMOS trigger output. Default level is 1.8 V

J8

TRIG_OUT_B

Adjustable level CMOS trigger output. Default level is 1.8 V

Содержание TSW14J56

Страница 1: ...ystem that captures and evaluates data samples from ADC EVMs and generates and sends desired test patterns to DAC EVMs Trademarks Windows is a trademark of Microsoft Corporation 1 Functionality The TS...

Страница 2: ...bps 10 routed transceiver channels 32 Gb DDR3 SDRAM split into four independent 512 164 Gb SDRAMs total of 512M samples each Quarter rate DDR3 controllers supporting up to 800 MHz operation 256K 16 bi...

Страница 3: ...Dynamically reconfigurable transceiver data rate Operating range from 0 600 to 12 5 Gbps Figure 2 shows a block diagram of the TSW14J56 EVM Figure 2 TSW14J56 EVM Block Diagram 1 1 ADC EVM Data Captur...

Страница 4: ...hat are stored inside the on board DDR3 memory To acquire data on a host PC the FPGA reads the data from memory and transmits parallel data to the on board high speed parallel to USB converter 1 2 DAC...

Страница 5: ...tion of the jumpers can be found in Table 2 Table 2 Jumper Description of the TSW14J56 Device Component Description Default SJP1 Power enable to general purpose 10 MHz oscillator Y1 1 to 2 SJP19 SJP21...

Страница 6: ...D27 On if VCCDDR_1 5 V is within specification D30 On if VTTDDR_0 75 V is within specification D34 On if VAR power is present D33 On if USB_1 2 V is within specification D28 On after FPGA completes c...

Страница 7: ...The connector pinout description is shown in Table 4 Table 4 FMC Connector Description of the TSW14J56 FMC Signal Name FMC Pin Standard JESD204 Application Mapping Description RX0_P N C6 and C7 Lane 0...

Страница 8: ...ound device clock Used for special FPGA functions such as sampling SYSREF LA01_P N_CC D8 and D9 DEVCLK C M Mezzanine bound device clock Used for low noise conversion clock SYSREF_P N G9 and G10 SYSREF...

Страница 9: ...inputs connected to the USB 3 0 controller With SJP14 18 in teh default postions this allows the FPGA to be programmed by the HSDC Pro software GUI Every time the TSW14J56EVM is powered down the FPGA...

Страница 10: ...ftware Follow all on screen instructions Accept the license agreements After the installer has finished click Next The GUI executable and associated files reside in the following directory C Program F...

Страница 11: ...the Instrument Option tab at the top left of the GUI and selecting Connect to the Board If this still does not correct this issue check the status of the host USB port When the software is installed...

Страница 12: ...ly reside in the directory called C Program Files x86 Texas Instruments High Speed Data Converter Pro 14J56revD Details Firmware To load a firmware after the GUI has established connection click the S...

Страница 13: ...s Guide available on www ti com If the message appears as shown in Figure 8 verify that all jumpers are in the default position and all power status LEDs are illuminated If certain jumpers are not ins...

Страница 14: ...rce in the USB Interface and Drivers section 10 Revision History Changes from A Revision November 2013 to B Revision Page Changed TSW14J56EVM Interfacing with an ADS42JB49EVM image 2 Changed TSW14J56...

Страница 15: ...TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD...

Страница 16: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments TSW14J56EVM...

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