Texas Instruments TSW14J56, Руководство пользователя

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Hardware Configuration
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8 SLWU086C – November 2013 – Revised January 2016
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TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
Table 4. FMC Connector Description of the TSW14J56 (continued)
FMC Signal Name FMC Pin Standard JESD204
Application Mapping
Description
TX6_P/N B36 and B37 Lane 6± (C
→
M) JESD Serial data transmitted from carrier and received by
mezzanine
TX7_P/N B32 and B33 Lane 7± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX8_P/N B28 and B29 Lane 8± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX9_P/N B24 and B25 Lane 9± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
GBTCLK0_M2C_P/N D4 and D5 DEVCLKA± (M → C) Primary carrier-bound reference clock required for FPGA
giga-bit transceivers. Equivalent to device clock.
GBTCLK1_M2C_P/N B20 and B21 Alt. DEVCLKA± (M → C) Alternate Primary Carrier-bound reference clock required for
FPGA giga-bit transceivers. For use when DEVCLKA (M
→
C) is not available
Device Clock, SYSREF, and SYNC
CLK_LA0_P/N G6 and G7 DEVCLKB± (M → C) Secondary carrier-bound device clock. Used for special FPGA
functions such as sampling SYSREF
LA01_P/N_CC D8 and D9 DEVCLK± (C → M) Mezzanine-bound device clock. Used for low noise
conversion clock
SYSREF_P/N G9 and G10 SYSREF± (M → C) Carrier-bound SYSREF signal
LA05_P/N D11 and D12 SYSREF± (C → M) Mezzanine-bound SYSREF signal
RX_SYNC_P/N G12 and G13 SYNC± (C → M) ADC mezzanine-bound SYNC signal for use in class 0/1/2
JESD204 systems
TX_SYNC_P/N F10 and F11 DAC SYNC± (M → C) Carrier-bound SYNC signal for use in class 0/1/2 JESD204
systems
TX_ALT_SYNC_P/N F19 and F20 Alt. DAC SYNC± (M → C) Alternate carrier-bound SYNC signal for use in class 0/1/2
JESD204B systems
RX_ALT_SYNC_P/N H31 and H32 Alt. SYNC± (C → M) Alternate ADC mezzanine-bound SYNC signal. For use when
SYNC (C
→ M) is not available
SYNC K22 DAC SYNC (M → C) Carrier-bound CMOS-level SYNC signal for use in class 0/1/2
JESD204 systems
Special Purpose I/O
PG_M2C_A F1 Power good from mezzanine to carrier
CLK0_M2C_P/N H4 and H5 GPIO clock
CLK1_M2C_P/N G2 and G3 GPIO clock
All other signals not mentioned in Table 4 can be used as general purpose I/O, either as single-ended
signals or differential pairs. The ANSI/VITA 57.1 standard assigns voltages to certain pins. These are
labeled as 12V, 3P3V, and VADJ nets on the connector page of the schematic. On the TSW14J56, these
pins are connected to test points to allow the user to provide voltages at these pin locations.