Functionality
2
SLWU086C – November 2013 – Revised January 2016
Copyright © 2013–2016, Texas Instruments Incorporated
TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
Figure 1. TSW14J56EVM Interfacing with an ADS58J63EVM
The major features of the TSW14J56 are:
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Subclasses: 0 (backward compatible), 1, 2
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Support for deterministic latency
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Serial lanes speeds up to 12.5 Gbps
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10 routed transceiver channels
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32 Gb DDR3 SDRAM (split into four independent 512×164 Gb SDRAMs, total of 512M samples each).
Quarter rate DDR3 controllers supporting up to 800-MHz operation
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256K 16-bit samples of internal FPGA memory
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Supports 1.8, 2.5 and 3-V adjustable CMOS IO standard
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Option for general purposed 10 MH oscillator
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Onboard UCD90120A for power sequencing and monitoring
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Onboard Cypress CYUSB301X USB 3.0 device for JTAG and parallel interface to the FPGA
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Reference clocking for transceivers available through FMC port or SMAs
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Supported by TI HSDC PRO software
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FPGA firmware developed with Quartus II 14.0 and QSYS
