Texas Instruments TSW14J56, Руководство пользователя

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+5 VDC Input
32Gb DDR III
RAM
ALTERA
Arria V GZ
(Firmware)
USB
to
Parallel
32 Bit 100 MHz
Parallel Interface
USB 3.0
Port
TSW14J56 EVM
ADC or DAC EVM
FMC Connector
JESD204B Interface
Data, Device CLK,
SYSREF, SYNC, GPIO
Power Sequencer/
Monitor
LDO and Switch
Regulators
www.ti.com
Functionality
3 SLWU086C – November 2013 – Revised January 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
– JESD RX IP core with support for:
• USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA configuration data accessible through USB and JTAG
• Lane alignment and character replacement enabled or disabled through USB and JTAG
– JESD TX IP core with support for:
• USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA data configured through USB and JTAG
• Character replacement enabled or disabled through USB and JTAG
– Dynamically reconfigurable transceiver data rate. Operating range from 0.600 to 12.5 Gbps
Figure 2 shows a block diagram of the TSW14J56 EVM.
Figure 2. TSW14J56 EVM Block Diagram
1.1 ADC EVM Data Capture
New TI high-speed ADCs and DACs now have high-speed serial data that meets the JESD204B standard.
These devices are generally available on an EVM that connects directly to the TSW14J56EVM. The
common connector between the EVMs and the TSW14J56EVM is a Samtec high-speed, high-density
FMC connector (SEAF-40-05.0-S-10-2-A-K) suitable for high-speed differential pairs up to 21 Gbps. A
common pinout for the connector across a family of EVMs has been established. At present, the interface
between the EVMs and the TSW14J56EVM has defined connections for 10 lanes of serial differential
data, two device clock pairs, two JESD204B SYSREF and SYNC pairs. There are four over-range single-
ended indicators, 12 spare general purpose CMOS I/O pins, and 29 spare differential LVDS or 58 single-
ended CMOS signals. The board has a spare SMA interface to the FPGA, 4 spare dip switches, a
pushbutton switch, several spare test points routed to the FPGA and 8 status LED's.