Functionality
4
SLWU086C – November 2013 – Revised January 2016
Copyright © 2013–2016, Texas Instruments Incorporated
TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
The data format for JESD204B ADCs and DACs is a serialized format, where individual bits of the data
are presented on the serial pairs commonly referred to as lanes. Devices designed around the JESD204B
spec can have up to 8 lanes for transmitting or receiving data. The firmware in the FPGA on the
TSW14J56 is designed to accommodate any of TI's ADC or DAC operating with any number of lanes from
1 to 8.
The GUI loads the FPGA with the appropriate firmware and a specific JESD204B configuration, based on
the ADC device selected in the device drop down window. Each ADC device that appears in this window
has an initialization file (.ini) associated to it. This .ini file contains JESD information, such as number of
lanes, number of converters, octets per frame, and other parameters. This information is loaded into the
FPGA registers after the user clicks on the capture button. After the parameters are loaded,
synchronization is established between the data converter and FPGA and valid data is then captured into
the on-board memory. See the High-Speed Data Capture Pro GUI Software User's Guide
and
section 2.3 in the guide for more information. Several .ini files are available to allow the user to load pre-
determined ADC JESD204B interfaces. For example, if the user selects the ADC called
"ADS42JB69_LMF_421", the FPGA will be configured to capture data from the ADS42JB69EVM with the
ADC JESD interface configured for 4 lanes, 2 converters, and 1 octet per frame.
The TSW14J56 device can capture up to 2G 16-bit samples at a maximum line rate of 12.5 Gbps that are
stored inside the on-board DDR3 memory. To acquire data on a host PC, the FPGA reads the data from
memory and transmits parallel data to the on-board high-speed parallel-to-USB converter.
1.2
DAC EVM Pattern Generator
In pattern generator mode, the TSW14J56EVM generates desired test patterns for DAC EVMs under test.
These patterns are sent from the host PC over the USB interface to the TSW14J56. The FPGA stores the
data received into the on-board DDR3 memory. The data from the memory is then read by the FPGA,
converted to JESD204B serial format, then transmitted to a DAC EVM. The TSW14J56 can generate
patterns up to 2G 16-bit samples at a line rate up to 12.5 Gbps.
The GUI comes with several existing test patterns that can be download immediately. The GUI also has a
pattern generation tool that allows the user to generate a custom pattern, then download it to the on-board
memory. See the High-Speed Data Capture Pro Software User's Guide
for more information.
Like the ADC capture mode, the DAC pattern generator mode uses .ini files to load predetermined
JESD204B interface information to the FPGA.
2
Hardware Configuration
This section describes the various portions of the TSW14J56EVM hardware.
2.1
Power Connections
The TSW14J56EVM hardware is designed to operate from a single supply voltage of +5 V DC. The power
input is controlled by the on and off switch, SW6. Make sure this switch is in the off position before
inserting the provided power cable. Insert the connector end of the power cable into J11 of the EVM.
Connect the positive red wire end of the power cable to +5V +/- 0.3VDC output of a +5VDC power supply
rated for at least 3 Amps. Connect the negative black wire to the RETURN or GND of the power supply.
The board can also be powered up by pro5 V DC to the red test point, TP34, and the return to any
black GND test point. The TSW14J56 draws approximately 0.6 A at power-up and 1.6 A when capturing 4
lanes of data from an ADS42JB69EVM at a line rate of 2.5 Gpbs.
