Texas Instruments TSW14J56, Руководство пользователя

Страница: 7 / 16

www.ti.com
Hardware Configuration
7 SLWU086C – November 2013 – Revised January 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator Card
User's Guide
J12 TRIG_OUT_C Adjustable level CMOS trigger output. Default level is 1.8 V
J3 REF_OSC_IN AC coupled spare input connected to FPGA CLK input
J14 EXT_SYSREFP Spare SYSREF positive input to FPGA
J15 EXT_SYSREFN Spare SYSREF negative input to FPGA
2.3.3.2 FPGA Mezzanine Card (FMC) Connector
The TSW14J56 EVM has one connector to allow for the direct plug in of TI JESD204B serial interface
ADC and DAC EVMs. The specifications for this connector are mostly derived from the ANSI/VITA 57.1
FPGA Mezzanine Card (FMC) Standard. This standard describes the compliance requirements for a low-
overhead protocol bridge between the IO of a mezzanine card and an FPGA processing device on a
carrier card. This specification is being used by FPGA vendors on their development platforms.
The FMC connector, J4, provides the interface between the TSW14J56EVM and the ADC or DAC EVM
under test. This 400-pin Samtec high-speed, high-density connector (part number SEAF-40-05.0-S-10-2-
A-K) is suitable for high-speed differential pairs up to 21 Gbps.
In addition to the JESD204B standard signals, several CMOS single-ended signals and LVDS differential
signals are connected between the FMC and FPGA. In the future, these signals may allow the HSDC Pro
GUI to control the SPI serial programming of ADC and DAC EVMs that support this feature. The
connector pinout description is shown in
Table 4 .
Table 4. FMC Connector Description of the TSW14J56
FMC Signal Name FMC Pin Standard JESD204
Application Mapping
Description
RX0_P/N C6 and C7 Lane 0± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX1_P/N A2 and A3 Lane 1± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX2_P/N A6 and A7 Lane 2± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX3_P/N A10 and A11 Lane 3± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX4_P/N A14 and A15 Lane 4± (M
→
C) JESD Serial data transmitted from mezzanine and received
by carrier
RX5_P/N A18 and A19 Lane 5± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX6_P/N B16 and B17 Lane 6± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX7_P/N B12 and B13 Lane 7± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX8_P/N B8 and B9 Lane 8± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX9_P/N B4 and B5 Lane 9± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
TX0_P/N C2 and C3 Lane 0± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX1_P/N A22 and A23 Lane 1± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX2_P/N A26 and A27 Lane 2± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX3_P/N A30 and A31 Lane 3± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX4_P/N A34 and A35 Lane 4± (C
→
M) JESD Serial data transmitted from carrier and received by
mezzanine
TX5_P/N A38 and A39 Lane 5± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine