Texas Instruments TSW14J56, Руководство пользователя

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Hardware Configuration
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6 SLWU086C – November 2013 – Revised January 2016
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TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
2.3 LEDs
2.3.1 Power and Configuration LEDs
Several LEDs are on the TSW14J56 EVM to indicate the presence of power and the state of the FPGA.
The description of these LEDs can be found in
Table 3 .
Table 3. Power and Configuration LED Description of the TSW14J56 Device
Component Description
D17 On if DDR3 VREF power is good
D10 On if 5V board power is present
D32 On if power monitor device indicates that a power net is out of tolerance
D11 On if +1.0 V is within specification
D13 On if VCCD_1.5 V is within specification
D16 On if VCC_1.5 V is within specification
D21 On if VCC_2.5 V is within specification
D23 On if VCCA_GXB_3.0 V is within specification
D25 On if VCC_PLL_2.5 V is within specification
D26 On if VCC_0.85V is within specification
D27 On if VCCDDR_1.5 V is within specification
D30 On if VTTDDR_0.75 V is within specification
D34 On if VAR power is present
D33 On if USB_1.2 V is within specification
D28 On after FPGA completes configuration
2.3.2 Status LEDs
Eight status LEDs on the TSW14J56EVM indicate the status of the FPGA, DDR3, and JESD204B
interface:
D1 – Indicates DAC EVM established SYNC with the TSW14J56 device when off
D2 – Indicates presence of device clock from DAC EVM when blinking
D3 – Indicates ADC EVM established SYNC with the TSW14J56 device when off
D4 – Indicates presence of device clock from ADC EVM when blinking
D5 – Not used
D6 – DDR3 initialization and calibration complete when off
D7 – DDR3 ready when off
D8 – DDR3 pass calibration and initialization if on
2.3.3 Connectors
2.3.3.1 SMA Connectors
The TSW14J56 has 9 SMA connectors. The connectors are defined below:
J6 GBTCLK0N Spare Transceiver reference clock negative input
J5 GBTCLK0P Spare Transceiver reference clock positive input
J13 TRIG_IN Adjustable level CMOS trigger input. Default level is 1.8 V
J7 TRIG_OUT_A Adjustable level CMOS trigger output. Default level is 1.8 V
J8 TRIG_OUT_B Adjustable level CMOS trigger output. Default level is 1.8 V