Texas Instruments TMS320C28x, Справочное руководство

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Pipelining of Instructions
4-2
4.1 Pipelining of Instructions
When executing a program, the C28x CPU performs these basic operations:
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Fetches instructions from program memory
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Decodes instructions
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Reads data values from memory or from CPU registers
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Executes instructions
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Writes results to memory or to CPU registers
For efficiency, the C28x performs these operations in eight independent
phases. Reads from memory are designed to be pipelined in two stages, which
correspond to the two pipeline phases used by the CPU for each memory-read
operation. At any time, there can be up to eight instructions being carried out,
each in a different phase of completion. Following are descriptions of the eight
phases in the order they occur. The address and data buses mentioned in
these descriptions are introduced in section 1.4.1 on page 1-9.
Fetch 1
(F1)
In the fetch 1 (F1) phase, the CPU drives a program-memory ad-
dress on the 22-bit program address bus, PAB(21:0).
Fetch 2
(F2)
In the fetch 2 (F2) phase, the CPU reads from program memory
by way of the program-read data bus, PRDB (31:0), and loads
the instruction(s) into an instruction-fetch queue.
Decode 1
(D1)
The C28x supports both 32-bit and 16-bit instructions and an
instruction can be aligned to an even or odd address. The
decode 1 (D1) hardware identifies instruction boundaries in the
instruction-fetch queue and determines the size of the next
instruction to be executed. It also determines whether the
instruction is a legal instruction.