Texas Instruments TMS320C28x, Справочное руководство

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CPU Architecture
2-2
2.1 CPU Architecture
All C28x devices contain a central processing unit (CPU), emulation logic, and
signals for interfacing with memory and peripherals. Included with these sig-
nals are three address buses and three data buses. Figure 2
− 1 shows the ma-
jor blocks and data paths of the C28x CPU. It does not reflect the actual silicon
implementation. The shaded buses are memory-interface buses that are ex-
ternal to the CPU. The operand bus supplies the values for multiplier, shifter,
and ALU operations, and the result bus carries the results to registers and
memory. The main blocks of the CPU are:
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Program and data control logic. This logic stores a queue of instructions
that have been fetched from program memory.
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Real-Time emulation and visibility
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Address register arithmetic unit (ARAU). The ARAU generates ad-
dresses for values that must be fetched from data memory. For a data
read, it places the address on the data-read address bus (DRAB); for a
data write, it loads the data-write address bus (DWAB). The ARAU also
increments or decrements the stack pointer (SP) and the auxiliary regis-
ters (XAR0, XAR1, XAR2, XAR3, XAR4, XAR5, XAR6, and XAR7).
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Atomic arithmetic logic unit (ALU). The 32-bit ALU performs 2s-com-
plement arithmetic and Boolean logic operations. Before doing its calcula-
tions, the ALU accepts data from registers, from data memory, or from the
program control logic. The ALU saves results to a register or to data
memory.
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Prefetch queue and instruction decode
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Address generators for program and data
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Fixed-point MPY/ALU . The multiplier performs 32-bit × 32-bit 2s-comple-
ment multiplication with a 64-bit result. In conjunction with the multiplier,
the ’28xx uses the 32-bit multiplicand register (XT), the 32-bit product reg-
ister (P), and the 32-bit accumulator (ACC). The XT register supplies one
of the values to be multiplied. The result of the multiplication can be sent
to the P register or to ACC.
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Interrupt processing