Texas Instruments TMS320C28x, Справочное руководство

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Pipelining of Instructions
4-5 Pipeline
(such as a branch or an interrupt) occurs, the queue is emptied. When the
instruction at the bottom of the queue reaches its D2 phase, that instruction
is passed to the instruction register for further decoding.
4.1.3 Address Counters FC, IC, and PC
Three program-address counters are involved in the fetching and execution
of instructions:
-
Fetch counter (FC). The fetch counter contains the address that is driven
on the program address bus (PAB) in the F1 pipeline phase. The CPU con-
tinually increments the FC until the queue is full or the queue is emptied
by a program-flow discontinuity. Generally, the FC holds an even address
and is incremented by 2, to accommodate 32-bit fetches. The only excep-
tion to this is when the code after a discontinuity begins at an odd address.
In this case, the FC holds the odd address. After performing a16-bit fetch
at the odd address, the CPU increments the FC by 1 and resumes 32-bit
fetching at even addresses.
-
Instruction counter (IC). After the D1 hardware determines the instruc-
tion size (16-bit or 32-bit), it fills the instruction counter (IC) with the ad-
dress of the next instruction to undergo D2 decoding. On an interrupt or
call operation, the IC value represents the return address, which is saved
to the stack, to auxiliary register XAR7, or to RPC.
-
Program counter (PC). When a new address is loaded into the IC, the
previous IC value is loaded into the PC. The program counter (PC) always
contains the address of the instruction that has reached its D2 phase.
Example 4 − 1 shows the relationship between the pipeline and the address
counters. Instruction 1 has reached its D2 phase (it has been passed to the
instruction register). The PC points to the address from which instruction 1
was taken (00
0050
16
). Instruction 2 has reached its D1 phase and will be
executed next (assuming no program-flow discontinuity flushes the instruc-
tion-fetch queue). The IC points to the address from which instruction 2 was
taken (00
0051
16
). Instruction 3 is in its F2 phase. It has been transferred to
the instruction-fetch queue but has not been decoded. Instructions 4 and 5 are
each in their F1 phase. The FC address (00
0054
16
) is being driven on the
PAB. During the next 32-bit fetch, Instructions 4 and 5 will be transferred from
addresses 00
0054
16
and 00 0055
16
to the queue.