Texas Instruments TMS320C28x, Справочное руководство

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Pipelining of Instructions
4-3 Pipeline
Decode 2
(D2)
The decode 2 (D2) hardware requests an instruction from the
instruction-fetch queue. The requested instruction is loaded into
the instruction register, where decoding is completed. Once an
instruction reaches the D2 phase, it runs to completion. In this
pipeline phase, the following tasks are performed:
-
If data is to be read from memory, the CPU generates the
source address or addresses.
-
If data is to be written to memory, the CPU generates the
destination address.
-
The address register arithmetic unit (ARAU) performs any
required modifications to the stack pointer (SP) or to an auxil-
iary register and/or the auxiliary register pointer (ARP).
-
If a program-flow discontinuity (such as a branch or an
illegal-instruction trap) is required, it is taken.
Read 1
(R1)
If data is to be read from memory, the read 1 (R1) hardware
drives the address(es) on the appropriate address bus(es).
Read 2
(R2)
If data was addressed in the R1 phase, the read 2 (R2) hardware
fetches that data by way of the appropriate data bus(es).
Execute
(E)
In the execute (E) phase, the CPU performs all multiplier, shifter,
and ALU operations. This includes all the prime arithmetic and
logic operations involving the accumulator and product register.
For operations that involve reading a value, modifying it, and writ-
ing it back to the original location, the modification (typically an
arithmetic or a logical operation) is performed during the E phase
of the pipeline. Any CPU register values used by the multiplier,
shifter, and ALU are read from the registers at the beginning of
the E phase. A result that is to be written to a CPU register is writ-
ten to the register at the end of the E phase.
Write
(W)
If a transferred value or result is to be written to memory, the write
occurs in the write (W) phase. The CPU drives the destination
address, the appropriate write strobes, and the data to be written.
The actual storing, which takes at least one more clock cycle, is
handled by memory wrappers or peripheral interface logic and is
not visible as a part of the CPU pipeline.