Texas Instruments TMS320C28x, Справочное руководство

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Memory Interface
1-9 Architectural Overview
1.4 Memory Interface
The C28x memory map is accessible outside the CPU by the memory inter-
face, which connects the CPU logic to memories, peripherals, or other inter-
faces. The memory interface includes separate buses for program space and
data space. This means an instruction can be fetched from program memory
while data memory is being accessed.
The interface also includes signals that indicate the type of read or write being
requested by the CPU. These signals can select a specified memory block or
peripheral for a given bus transaction. In addition to 16-bit and 32-bit ac-
cesses, the C28x supports special byte-access instructions which can access
the least significant byte (LSByte) or most significant byte (MSByte) of an ad-
dressed word. Strobe signals indicate when such an access is occurring on
a data bus.
1.4.1 Address and Data Buses
The memory interface has three address buses:
PAB Program address bus. The PAB carries addresses for reads and
writes from program space. PAB is a 22-bit bus.
DRAB Data-read address bus. The 32-bit DRAB carries addresses for
reads from data space.
DWAB Data-write address bus. The 32-bit DWAB carries addresses for
writes to data space.
The memory interface also has three data buses:
PRDB Program-read data bus. The PRDB carries instructions or data dur-
ing reads from program space. PRDB is a 32-bit bus.
DRDB Data-read data bus. The DRDB carries data during reads from data
space. PRDB is a 32-bit bus.
DWDB Data-/Program-write data bus. The 32-bit DWDB carries data during
writes to data space or program space.