Chapter 4: Software
R-Engine-D
4-6
−
Sets up
PCS5-6
lines as chip-select lines, with three wait state operation.
outport(0xffa8, 0xa0bf); // s8, 3 wait states
outport(0xffa6, 0x81ff); // CS0MSKH
•
Initialize PACS so that
PCS0-PCS3
are configured so that:
−
Sets up
PCS0-3
lines as chip-select lines, with fifteen wait state operation.
−
The chip select lines starts at I/O address 0x0000, with each successive chip select line
addressed 0x100 higher in I/O space.
outport(0xffa4, 0x007f); // CS0MSKL, 512K, enable CS0 for RAM
•
Configure the two PIO ports for default operation. All pins are set up as default input, except for
P29 (used for driving the LED), and peripheral function pins for SER0, as well as chip selects for
the PPI.
outport(0xff78,0xe73c); // PDIR1, TxD0, RxD0, TxD1, RxD1,
// P16=PCS0, P17=PCS1=PPI
outport(0xff76,0x0000); //
PIOM1
outport(0xff72,0xec7b);
// PDIR0, P12,A19,A18,A17,P2=PCS6=RTC
outport(0xff70,0x1000);
// PIOM0, P12=LED
•
Configure the PPI 82C55 to all inputs. You can reset these to inputs.
outportb(0x0103,0x9a);
// all pins are input, I20-23 output
outportb(0x0100,0);
outportb(0x0101,0);
outportb(0x0102,0x01);
// I20 high
The chip select lines are set to 15 wait states, by default. This makes it possible to interface with many
slower external peripheral components. If you require faster I/O access, you can modify this number down
as needed. Some TERN components, such as the Real-Time-Clock, might fail if the wait state is decreased
too dramatically. A function is provided for this purpose.
void io_wait
Arguments:
char wait
Return value:
none.
This function sets the current wait state depending on the argument
wait
.
wait=0, wait states = 0, I/O enable for 100 ns
wait=1, wait states = 1, I/O enable for 100+25 ns
wait=2, wait states = 2, I/O enable for 100+50 ns
wait=3, wait states = 3, I/O enable for 100+75 ns
wait=4, wait states = 5, I/O enable for 100+125 ns
wait=5, wait states = 7, I/O enable for 100+175 ns
wait=6, wait states = 9, I/O enable for 100+225 ns
wait=7, wait states = 15, I/O enable for 100+375 ns
4.3.2
External Interrupt Initialization
There are up to six external interrupt sources on the R-Engine-D, consisting of five maskable interrupt pins
(
INT4-INT0
) and one non-maskable interrupt (
NMI
). There are also an additional eight internal interrupt
sources not connected to the external pins, consisting of three timers, two DMA channels, both
asynchronous serial ports, and the
NMI
from the watchdog timer. For a detailed discussion involving the
ICUs, the user should refer to Chapter 7 of the AMD Am186ER Microcontroller User’s Manual. Or the
R1100 user’s manual, both available on the CD under the
amd_docs
directory. (
Remember, DMA
channels to and from the serial port not available on the R1100.)
TERN provides functions to enable/disable all of the 6 external interrupts. The user can call any of the
interrupt init functions listed below for this purpose. The first argument indicates whether the particular
