R-Engine-D
Chapter 1: Introduction
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Up to 1GB memory expansion via CompactFlash interface
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3 serial ports (1 from Am186ER, plus two from SCC2692 UART) support full-duplex 7, 8 or 9-bit
asynchronous communication (only SCC2692 supports 9-bit)
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14 sinking / 16 sourcing high voltage drivers
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2 high-speed PWM outputs
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6 external interrupt inputs, 3 16-bit timer/counters
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32 multifunctional I/O lines from Am186ER
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24 bi-directional I/O lines from 82C55 PPI
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512-byte serial EEPROM
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Supervisor chip (691) for reset and watchdog
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Real-time clock (DS1337), lithium coin battery*
* = optional
1.4
Physical Description
The physical layout of the R-Engine-D is shown below.
J1 Header
Address / Data
Expansion Bus
8-ch.
16-bit
ADC
Dual 2-ch.
12-bit DAC
4-ch. 12-bit
DAC 200KHz
8-ch. 12
ADC 300KHz
Step 2 Jumper
J2 pins 38 & 40
SCC2692
Dual UART
J2 Header
Interrupts, PIOs
+12V
Input
J3, J4 Header
ADC, DAC, PPI I/O
PPI
24 bi-directional
TTL level I/Os
Flash & SRAM
Up to 256KW of each
High voltage
drivers
CS8900
Ethernet controller
SER0
(Debug serial port)
1-3