R-Engine-D
Chapter 3:
3-15
Hardware
H4
H3
J2
H2
J1
J4
J3
Figure 3.5 Pin 1 locations for RD headers
J2 Signal
GND
40 39 VCC
P4 38 37 P14
IP0 36 35 P6
TxD0
34 33
RxD0
32 31 P19
P5 30 29 P1
TxDA
28 27 P2
RxDA
26 25
IP1 24 23 P15
IP2 22 21 INT3
P0 20 19 INT2
P25 18 17 P24
IP3 16 15 IP4
P11 14 13 P18
P10 12 11 P13
A19 10 9 P23
/INT0
8 7 NMI
/INT1 6
5
SCLK
P26 4 3 SDAT
GND
2 1 OP0
J1 Signal
VCC 1 2
GND
OP1 3 4
CLK
RxDB 5 6
GND
TxDB 7 8
D0
VOFF
9
10
D1
/BHE 11 12 D2
D15 13
14
D3
/RST 15
16
D4
RST 17
18
D5
P16 19
20
D6
D14 21
22
D7
D13 23
24
GND
/HB 25
26
P12
D12 27
28
A7
/WR
29
30
A6
/RD 31
32
A5
D11 33
34
A4
D10 35
36
A3
D9 37
38
A2
D8 39
40
A1
Table 3.3 Signals for J2 and J1, 20x2 expansion ports