Terasic De0-Nano, Руководство пользователя

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The DE0-Nano Control Panel is based on a Nios II SOPC system instantiated in the Cyclone IV E
FPGA with software running on the on-chip memory. The software part is implemented in C code;
the hardware part is implemented in Verilog HDL code with SOPC builder. The source code is not
available on the DE0-Nano System CD.
To run the Control Panel, users should make the configuration according to Section 4.1. Figure 4-8
depicts the structure of the Control Panel. Each input/output device is controlled by the Nios II
Processor instantiated in the FPGA chip. The communication with the PC is done via the USB
Blaster link. The Nios II interprets the commands sent from the PC and performs the corresponding
actions.
Figure 4-8 The block diagram of the DE0-Nano Control Panel