Sun Oracle Fire X4470 M2, Руководство по обслуживанию

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1-4 Sun Server X2-4 Service Manual • April 2013
Features of each Intel Xeon Processor E7-4800 Series include:
■
Up to ten cores with Hyper-Threading (two threads/core)
■
Up to 30MB shared last level cache
■
32nm process technology
■
Two integrated memory controllers with four Intel Scalable Memory Interconnects
(SMI channels)
■
Supports speeds of DDR3-1067 MT/s via an Intel 7510 Scalable Memory Buffer
■
Four full-width, bidirectional Intel QuickPath interconnects (QPI links)
■
6.4 GT/s (12.8 GB/s per direction)
■
Automatic self-healing by degrading to half-width or quarter-width link
operation
■
CPU Thermal Design Power (TDP) of 105W or 130W
Note –
For more information about Intel QuickPath Interconnects, refer to Weaving
High Performance Multiprocessor Fabric from Intel Press at
http://www.intel.com/intelpress/sum_qpi.htm
.
1.1.4 Memory
Each CPU in the Sun Server X2-4 has four SMI channels leading to Intel 7510 Scalable
Memory Buffers (located on two memory risers). Each memory buffer has an SMI
link to the CPU and two DDR3 interfaces. Each SMI interface can operate at speeds
of 6.4 GT/s, which correspond to DDR3 operation at 1067 MT/s. From the CPU to
the Intel 7510 Scalable Memory Buffer, the SMI interface supports 11 lanes (9 data + 1
CRC + 1 spare). From the Intel 7510 Scalable Memory Buffer to the CPU, the SMI
interface supports 14 lanes (12 data + 1 CRC + 1 spare). The CPU retries memory
transactions that incur a CRC error. For persistent errors, the SMI link has spare lanes
for automatic self-healing.
The system supports a maximum of eight memory risers (4 CPU configuration) or
four memory risers (2 CPU configuration). Each riser houses 8 DIMM slots for the
four DDR3 channels. The system can operate with 0, 2, 4, 6 or 8 DIMMs on a given
riser. For maximum performance, install at least two ranks of DIMMs on every
available DDR3 channel (for example, 4 DIMMs per riser with two risers per CPU).
Each of two memory controllers in a CPU operates its two SMI channels as a
lock-step pair. The memory controller treats each pair of DDR3 channels behind the
two memory buffers as a 144-bit-wide DRAM interface. As a result, the DIMMs must
be installed in pairs, with identical DIMMs in each pair.
The DDR3 interfaces include the following features: