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DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

103

6.3.11 Electrical

sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up
performance:

•

A supply overvoltage is applied to each power supply pin

•

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

6.3.12 I/O

current

injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V

SS

or

above V

DD

(for standard pins) should be avoided during normal product operation.

However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Table 39. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class

Maximum

value

(1)

1. Based on characterization results, not tested in production.

Unit

V

ESD(HBM)

Electrostatic discharge
voltage (human body model)

T

A

=

+25 °C, conforming to

JESD22-A114

2

2000

V

V

ESD(CDM)

Electrostatic discharge
voltage (charge device
model)

T

A

= +25 °C, conforming to

ANSI/ESD STM5.3.1

II

500

Table 40. Electrical sensitivities

Symbol

Parameter

Conditions

Class

LU

Static latch-up class

T

A

=

+105 °C conforming to JESD78A

II level A

«
...
77
78
79
80
81
...
»

Содержание STM32L151C6

Страница 1: ...debug supported JTAG and trace supported Up to 83 fast I Os 73 I Os 5V tolerant all mappable on 16 external interrupt vectors Memories Up to 128 KB Flash with ECC Up to 16 KB RAM Up to 4 KB of true E...

Страница 2: ...wer supply schemes 18 3 3 2 Power supply supervisor 18 3 3 3 Voltage regulator 19 3 3 4 Boot modes 19 3 4 Clock management 20 3 5 Low power real time clock and backup registers 22 3 6 GPIOs general pu...

Страница 3: ...criptions 30 5 Memory mapping 46 6 Electrical characteristics 47 6 1 Parameter conditions 47 6 1 1 Minimum and maximum values 47 6 1 2 Typical values 47 6 1 3 Typical curves 47 6 1 4 Loading capacitor...

Страница 4: ...3 14 NRST pin characteristics 84 6 3 15 TIM timer characteristics 85 6 3 16 Communication interfaces 86 6 3 17 12 bit ADC characteristics 92 6 3 18 DAC electrical specifications 98 6 3 19 Temperature...

Страница 5: ...58 Table 20 Current consumption in Low power run mode 60 Table 21 Current consumption in Low power sleep mode 61 Table 22 Typical and maximum current consumptions in Stop mode 62 Table 23 Typical and...

Страница 6: ...aracteristics 102 Table 62 LCD controller characteristics 103 Table 63 LQPF100 14 x 14 mm 100 pin low profile quad flat package mechanical data 106 Table 64 LQFP64 10 x 10 mm 64 pin low profile quad f...

Страница 7: ...e and CPHA 1 1 89 Figure 24 SPI timing diagram master mode 1 90 Figure 25 USB timings definition of data signal rise and fall time 91 Figure 26 ADC accuracy characteristics 95 Figure 27 Typical connec...

Страница 8: ...ly suitable for a wide range of applications Medical and handheld equipment Application control and user interface PC peripherals gaming GPS and sport equipment Alarm systems Wired and wireless sensor...

Страница 9: ...ces contain standard and advanced communication interfaces up to two I2 Cs and SPIs three USARTs and a USB The STM32L15xx6 8 B devices offer up to 20 capacitive sensing channels to simply add touch se...

Страница 10: ...interfaces SPI 2 I2 C 2 USART 3 USB 1 GPIOs 37 51 83 12 bit synchronized ADC Number of channels 1 14 channels 1 20 channels 1 24 channels 12 bit DAC Number of channels 2 2 LCD STM32L152xx Only COM x...

Страница 11: ...es and ARM Cortex M3 core for STM32L family In addition specific care for the design architecture has been taken to optimize the mA DMIPS and mA MHz ratios This allows the ultralow power performance t...

Страница 12: ...d E d Z d d K EZ d s s s h W h D DK D K E t h W D s D WD s Z W D d D d D y d K D yd K E K Khd K Khd K E W W D W W W sK d Z s K Z WK t Z d D D Zd Z h Z D h Zd h Zd W Zy d y d Zd h Zd d s Z D t s s s s...

Страница 13: ...the clock frequency and the number of enabled peripherals are both limited Low power run mode consumption refer to Table 20 Current consumption in Low power run mode Low power sleep mode This mode is...

Страница 14: ...Alarm A or Alarm B RTC tamper event RTC timestamp event or RTC Wakeup event occurs Standby mode without RTC Standby mode is used to achieve the lowest power consumption The internal voltage regulator...

Страница 15: ...For example to switch from 4 2 MHz to 32 MHz you can switch from 4 2 MHz to 16 MHz wait 5 s then switch from 16 MHz to 32 MHz 2 Should be USB compliant from I O voltage standpoint the minimum VDD is...

Страница 16: ...Y Y EEPROM Y Y Y Y Brown out rest BOR Y Y Y Y Y Y Y DMA Y Y Y Y Programmable Voltage Detector PVD Y Y Y Y Y Y Y Power On Reset POR Y Y Y Y Y Y Y Power Down Rest PDR Y Y Y Y Y Y High Speed Internal HSI...

Страница 17: ...different regions and an optional predefined background region Owing to its embedded ARM core the STM32L15xx6 8 B is compatible with all ARM tools and software DAC Y Y Y Y Y Temperature sensor Y Y Y Y...

Страница 18: ...ough VDD pins VSSA VDDA 1 65 to 3 6 V external analog power supplies for ADC reset blocks RCs and PLL minimum voltage to be applied to VDDA is 1 8 V when the ADC is used VDDA and VSSA must be connecte...

Страница 19: ...An interrupt can be generated when VDD VDDA drops below the VPVD threshold and or when VDD VDDA is higher than the VPVD threshold The interrupt service routine can then generate a warning message and...

Страница 20: ...the system LSE the MSI frequency can be trimmed by software down to a 0 5 accuracy Auxiliary clock source two ultralow power clock sources that can be used to drive the LCD controller and the real tim...

Страница 21: ...CK NABLE NABLE 0ERIPHERAL LOCK Z MAX Z MAX TO ORTEX 3YSTEM TIMER LOCK NABLE 393 4 X 4 X ORTEX FREE RUNNING CLOCK TO 4 AND F 0 PRESCALER X ELSE X F 0 PRESCALER X ELSE X Z MAX 3 3 Z 3 3 54 3 2 Z X X X X...

Страница 22: ...6 GPIOs general purpose inputs outputs Each of the GPIO pins can be configured by software as output push pull or open drain as input with or without pull up or pull down or as peripheral alternate fu...

Страница 23: ...ct memory access The flexible 7 channel general purpose DMA is able to manage memory to memory peripheral to memory and memory to peripheral transfers The DMA controller supports circular buffer manag...

Страница 24: ...ure sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value The sensor provides good linearity but it has to be calibrated...

Страница 25: ...fast or slow mode The threshold can be one of the following DAC output External I O Internal reference voltage VREFINT or VREFINT submultiple 1 4 1 2 3 4 Both comparators can wake up from Stop mode a...

Страница 26: ...uch sensing firmware library 3 15 Timers and watchdogs The ultralow power STM32L15xx6 8 B devices include six general purpose timers two basic timers and two watchdog timers Table 6 compares the featu...

Страница 27: ...y include a 16 bit prescaler TIM10 and TIM11 feature one independent channel whereas TIM9 has two independent channels for input capture output compare PWM or one pulse mode output They can be synchro...

Страница 28: ...able to communicate at speeds of up to 4 Mbit s They provide hardware management of the CTS and RTS signals They support IrDA SIR ENDEC are ISO 7816 compliant and have LIN Master Slave capability All...

Страница 29: ...l wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK respectively and a specific sequence...

Страница 30: ...lout 1 This figure shows the package top view AI F 0 3 26 B 1 3 26 B287 3 3 83 3 26 B287 3 966 95 95 9 3 3 3 3 8 3 9 966B 9 B 1567 3 3 3 83 3 3 3 3 966B 966B 9 B 3 3 3 3 227 3 9 B 3 3 3 3 3 3 3 3 3 3...

Страница 31: ...PA13 PA12 PA11 PA10 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 V...

Страница 32: ...4 OSC32_IN PA7 PA4 PA2 PA15 PB11 PB1 PA6 PA3 H PB10 PC5 PC4 D PA8 PA9 BOOT0 PB8 C PC9 PA11 PB6 PC12 VDDA PB9 B PA12 PC10 PC15 OSC32_OUT PB3 PD2 A 8 7 6 5 4 3 2 1 VSS_4 OSC_IN OSC_OUT VDD_4 G F E PC2 V...

Страница 33: ...PC3 VSSA VDDA PA0 WKUP1 PA1 PA2 VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4...

Страница 34: ...B 34 129 DocID17659 Rev 10 Figure 8 STM32L15xCx UFQFPN48 pinout 1 This figure shows the package top view 6 33 4 0 0 0 0 0 0 0 6 633 0 5 1 0 0 633 0 6 0 0 7 50 0 0 0 0 6 0 0 0 0 0 0 0 0 6 33 AI D 0 0 0...

Страница 35: ...actual pin name Pin type S Supply pin I Input only pin I O Input output pin I O structure FT 5 V tolerant I O TC Standard 3 3 V I O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak...

Страница 36: ...C13 WKUP2 I O FT PC13 RTC_TAMP1 RTC_TS RTC_OUT WKUP2 8 3 A1 D1 3 PC14 OSC32_IN 4 I O TC PC14 OSC32_IN 9 4 B1 E1 4 PC15 OSC32_OUT 4 I O TC PC15 OSC32_OUT 10 F2 VSS_5 S VSS_5 11 G2 VDD_5 S VDD_5 12 5 C1...

Страница 37: ...ADC_IN7 TIM3_CH2 LCD_SEG4 TIM11_CH1 COMP1_INP 33 24 H5 K5 PC4 I O FT PC4 ADC_IN14 LCD_SEG22 COMP1_INP 34 25 H6 L5 PC5 I O FT PC5 ADC_IN15 LCD_SEG23 COMP1_INP 35 26 F5 M5 18 PB0 I O TC PB0 ADC_IN8 TIM...

Страница 38: ...P1_INP TIM11_CH1 RTC_REFIN 55 K9 PD8 I O FT PD8 USART3_TX LCD_SEG28 56 K8 PD9 I O FT PD9 USART3_RX LCD_SEG29 57 J12 PD10 I O FT PD10 USART3_CK LCD_SEG30 58 J11 PD11 I O FT PD11 USART3_CTS LCD_SEG31 59...

Страница 39: ...FT PC11 USART3_RX LCD_SEG29 LCD_SEG41 LCD_COM5 80 53 C5 B10 PC12 I O FT PC12 USART3_CK LCD_SEG30 LCD_SEG42 LCD_COM6 81 C9 PD0 I O FT PD0 SPI2_NSS TIM9_CH1 82 B9 PD1 I O FT PD1 SPI2_SCK 83 54 B5 C8 PD2...

Страница 40: ...his pin should be connected to VDD 4 The PC14 and PC15 I Os are only configured as OSC32_IN OSC32_OUT when the LSE oscillator is on by setting the LSEON bit in the RCC_CSR register The LSE oscillator...

Страница 41: ...T2_ CTS TIMx_IC1 EVENTOUT PA1 TIM2_CH2 USART2_ RTS SEG0 TIMx_IC2 EVENTOUT PA2 TIM2_CH3 TIM9_CH1 USART2_ TX SEG1 TIMx_IC3 EVENTOUT PA3 TIM2_CH4 TIM9_CH2 USART2_ RX SEG2 TIMx_IC4 EVENTOUT PA4 SPI1_NSS U...

Страница 42: ...SEG16 EVENTOUT PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA COM3 EVENTOUT PB10 TIM2_CH3 I2C2_SCL USART3_ TX SEG10 EVENTOUT PB11 TIM2_CH4 I2C2_SDA USART3_ RX SEG11 EVENTOUT PB12 TIM10_CH1 I2C2_ SMBA SPI2_NSS USART...

Страница 43: ...3_ TX COM4 SEG28 SEG40 TIMx_IC3 EVENTOUT PC11 USART3_ RX COM5 SEG29 SEG41 TIMx_IC4 EVENTOUT PC12 USART3_ CK COM6 SEG30 SEG42 TIMx_IC1 EVENTOUT PC13 WKUP2 RTC_TAMP1 RTC_TS RTC_OUT WKUP2 TIMx_IC2 EVENTO...

Страница 44: ...IC1 EVENTOUT PD9 USART3_ RX TIMx_IC2 EVENTOUT PD10 USART3_ CK TIMx_IC3 EVENTOUT PD11 USART3_ CTS TIMx_IC4 EVENTOUT PD12 TIM4_CH1 USART3_ RTS TIMx_IC1 EVENTOUT PD13 TIM4_CH2 TIMx_IC2 EVENTOUT PD14 TIM4...

Страница 45: ...x_IC2 EVENTOUT PE10 TIM2_CH2 TIMx_IC3 EVENTOUT PE11 TIM2_CH3 TIMx_IC4 EVENTOUT PE12 TIM2_CH4 SPI1_NSS TIMx_IC1 EVENTOUT PE13 SPI1_SCK TIMx_IC2 EVENTOUT PE14 SPI1_MISO TIMx_IC3 EVENTOUT PE15 SPI1_MOSI...

Страница 46: ...sh Interface reserved reserved reserved 0x4000 6200 0x4000 7000 0x4000 7400 0x4000 7C00 0x4001 0400 0x4002 3C00 0x4002 4000 0x4002 6000 0x4002 6400 0x6000 0000 0xE010 0000 reserved 0xFFFF FFFF USB Reg...

Страница 47: ...to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 Please refer to device ErrataSheet for possible latest changes of electrical characteristics 6 1 2...

Страница 48: ...Figure 12 Power supply scheme Figure 10 Pin loading conditions Figure 11 Pin input voltage 06 9 S 0 8 SLQ 06 9 0 8 SLQ 9 1 06 9 9 1 QDORJ 5 V 3 3 2V 287 1 HUQHO ORJLF 38 LJLWDO 0HPRULHV 6WDQGE SRZHU F...

Страница 49: ...source VSEL switch is open 2 Option 2 LCD power supply is provided by the internal step up converter VSEL switch is closed an external capacitance is needed for correct behavior of this converter 6 1...

Страница 50: ...VDDA 0 4 V VESD HBM Electrostatic discharge voltage human body model see Section 6 3 11 Table 11 Current characteristics Symbol Ratings Max Unit IVDD Total current into VDD VDDA power lines source 1...

Страница 51: ...AC used 1 8 3 6 VIN Input voltage on FT pins 3 Input voltage on BOOT0 pin Input voltage on any other pin 2 0 V VDD 3 6 V 1 65 V VDD 2 0 V 0 3 0 3 0 0 3 5 5 5 25 5 5 VDD 0 3 V PD Power dissipation at T...

Страница 52: ...ime rate BOR detector enabled 20 BOR detector disabled 0 1000 TRSTTEMPO 1 Reset temporization VDD rising BOR enabled 2 3 3 ms VDD rising BOR disabled 2 0 4 0 7 1 6 VPOR PDR Power on power down reset t...

Страница 53: ...8 VPVD4 PVD threshold 4 Falling edge 2 57 2 64 2 69 Rising edge 2 68 2 74 2 79 VPVD5 PVD threshold 5 Falling edge 2 77 2 83 2 88 Rising edge 2 87 2 94 2 99 VPVD6 PVD threshold 6 Falling edge 2 97 3 05...

Страница 54: ...due to ADC and VDDA VREF values 5 mV TCoeff 3 Temperature coefficient 40 C TJ 105 C 20 50 ppm C 0 C TJ 50 C 20 ACoeff 3 Long term stability 1000 hours T 25 C 1000 ppm VDDCoeff 3 Voltage coefficient 3...

Страница 55: ...n values are derived from the tests performed under ambient temperature TA 25 C and VDD supply voltage conditions summarized in Table 13 General operating conditions unless otherwise specified The MCU...

Страница 56: ...z 470 600 600 600 4 MHz 890 1025 1025 1025 Range 2 VCORE 1 5 V VOS 1 0 10 4 MHz 1 1 3 1 3 1 3 mA 8 MHz 2 2 5 2 5 2 5 16 MHz 3 9 5 5 5 Range 1 VCORE 1 8 V VOS 1 0 01 8 MHz 2 16 3 3 3 16 MHz 4 8 5 5 5 5...

Страница 57: ...00 500 500 4 MHz 720 860 860 860 3 Range 2 VCORE 1 5 V VOS 1 0 10 4 MHz 0 9 1 1 1 mA 8 MHz 1 65 2 2 2 16 MHz 3 2 3 7 3 7 3 7 Range 1 VCORE 1 8 V VOS 1 0 01 8 MHz 2 2 5 2 5 2 5 16 MHz 4 4 5 4 5 4 5 32...

Страница 58: ...clock source 16 MHz Range 2 VCORE 1 5 V VOS 1 0 10 16 MHz 1000 1100 1100 1100 Range 1 VCORE 1 8 V VOS 1 0 01 32 MHz 2300 2500 2500 2500 MSI clock 65 kHz Range 3 VCORE 1 2 V VOS 1 0 11 65 kHz 30 50 50...

Страница 59: ...V VOS 1 0 11 65 kHz 40 70 70 80 A MSI clock 524 kHz 524 kHz 60 90 90 100 MSI clock 4 2 MHz 4 2 MHz 210 250 250 260 1 Based on characterization not tested in production unless otherwise specified 2 Osc...

Страница 60: ...C 37 42 TA 55 C 37 42 TA 85 C 37 42 TA 105 C 48 65 All peripherals OFF code executed from Flash VDD from 1 65 V to 3 6 V MSI clock 65 kHz fHCLK 32 kHz TA 40 C to 25 C 24 32 TA 85 C 33 42 TA 105 C 48 6...

Страница 61: ...N TA 40 C to 25 C 17 5 25 TA 85 C 22 27 TA 105 C 31 39 MSI clock 65 kHz fHCLK 65 kHz Flash ON TA 40 C to 25 C 18 26 TA 85 C 23 28 TA 105 C 31 40 MSI clock 131 kHz fHCLK 131 kHz Flash ON TA 40 C to 25...

Страница 62: ...ty 3 TA 40 C to 25 C 3 3 6 TA 55 C 4 5 8 TA 85 C 6 6 12 TA 105 C 13 6 27 LCD ON 1 8 duty 4 TA 40 C to 25 C 7 7 10 TA 55 C 8 6 12 TA 85 C 10 7 16 TA 105 C 19 8 40 RTC clocked by LSE external clock 32 7...

Страница 63: ...ax values are given for VDD 3 6 V unless otherwise specified 2 Based on characterization not tested in production unless otherwise specified 3 LCD enabled with external VLCD static duty division ratio...

Страница 64: ...TA 40 C to 25 C VDD 1 8 V 0 9 A TA 40 C to 25 C 1 1 1 8 TA 55 C 1 42 2 5 TA 85 C 1 87 3 TA 105 C 2 78 5 RTC clocked by LSE no independent watchdog 3 TA 40 C to 25 C VDD 1 8 V 1 TA 40 C to 25 C 1 33 2...

Страница 65: ...Low power sleep and run APB1 TIM2 13 10 5 8 10 5 A MHz fHCLK TIM3 14 12 9 12 TIM4 12 5 10 5 8 11 TIM6 5 5 4 5 3 5 4 5 TIM7 5 5 5 3 5 4 5 LCD 5 5 5 3 5 5 WWDG 4 3 5 2 5 3 5 SPI2 5 5 5 4 5 USART2 9 8 5...

Страница 66: ...z Range 3 fHCLK 64kHz Low power run sleep fAPB1 fHCLK fAPB2 fHCLK default prescaler value for each peripheral The CPU is in Sleep mode in both cases No I O pins toggling Not tested in production 2 HSI...

Страница 67: ...d in Table 13 Table 25 Low power mode wakeup timings Symbol Parameter Conditions Typ Max 1 1 Based on characterization not tested in production unless otherwise specified Unit tWUSLEEP Wakeup from Sle...

Страница 68: ...iagram Figure 15 High speed external clock source AC timing diagram Table 26 High speed external user clock characteristics 1 1 Guaranteed by design not tested in production Symbol Parameter Condition...

Страница 69: ...s specified in Table 28 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabil...

Страница 70: ...cterization results not tested in production Symbol Parameter Conditions Min Typ Max Unit fOSC_IN Oscillator frequency 1 24 MHz RF Feedback resistor 200 k C Recommended load capacitance versus equival...

Страница 71: ...ion Symbol Parameter Conditions Min Typ Max Unit fLSE Low speed external oscillator frequency 32 768 kHz RF Feedback resistor 1 2 M C 2 2 Refer to the note and caution paragraphs below the table and t...

Страница 72: ...ce CL has the following formula CL CL1 x CL2 CL1 CL2 Cstray where Cstray is the pin capacitance and board or trace PCB related capacitance Typically it is between 2 pF and 7 pF Caution To avoid exceed...

Страница 73: ...of 16 0 4 0 7 Trimming code is a multiple of 16 1 5 ACCHSI 2 2 Based on characterization not tested in production Accuracy of the factory calibrated HSI oscillator VDDA 3 0 V TA 25 C 1 3 3 Tested in...

Страница 74: ...MSI range 5 2 1 MSI range 6 4 2 ACCMSI Frequency error after factory calibration 0 5 DTEMP MSI 1 MSI oscillator frequency drift 0 C TA 85 C 3 DVOLT MSI 1 MSI oscillator frequency drift 1 65 V VDD 3 6...

Страница 75: ...ion for an individual part once the initial frequency has been measured 2 Based on characterization not tested in production Table 32 MSI oscillator characteristics continued Symbol Parameter Conditio...

Страница 76: ...ithout losing data stored in RAM in Stop mode or under Reset or in hardware registers only in Stop mode STOP mode or RESET 1 65 V Table 35 Flash memory and data EEPROM characteristics Symbol Parameter...

Страница 77: ...are based on the EMS levels and classes defined in application note AN1709 Table 36 Flash memory data EEPROM endurance and data retention Symbol Parameter Conditions Value Unit Min 1 1 Based on chara...

Страница 78: ...eset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on...

Страница 79: ...input output and configurable I O pin These tests are compliant with EIA JESD 78A IC latch up standard 6 3 12 I O current injection characteristics As a general rule current injection to the I O pins...

Страница 80: ...failure is indicated by an out of range parameter ADC error out of spec current injection on adjacent pins or other functional failure for example reset oscillator frequency deviation LCD levels etc...

Страница 81: ...Os with analog switches 50 VSS VIN VDD I Os with analog switches and LCD 50 VSS VIN VDD I Os with USB TBD FT I O VDD VIN 5V TBD VSS VIN VDD Standard I Os 50 RPU Weak pull up equivalent resistor 6 1 V...

Страница 82: ...from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 13 All I Os are CMOS and TTL compliant Table 43 Output voltage characteristics Symbol Parameter Co...

Страница 83: ...m frequency 3 CL 50 pF VDD 2 7 V to 3 6 V 2 MHz CL 50 pF VDD 1 65 V to 2 7 V 1 tf IO out tr IO out Output rise and fall time CL 50 pF VDD 2 7 V to 3 6 V 125 ns CL 50 pF VDD 1 65 V to 2 7 V 250 10 Fmax...

Страница 84: ...UTY CYCLE IS WHEN LOADED BY P 4 TF OUT Table 45 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL NRST 1 1 Guaranteed by design not tested in production NRST input low level vo...

Страница 85: ...the input output alternate function characteristics output compare input capture external clock PWM output AI 34 XX 205 234 6 ILTER NTERNAL RESET XTERNAL RESET CIRCUIT Table 46 TIMx 1 characteristics...

Страница 86: ...I2 C 1 1 Guaranteed by design not tested in production Fast mode I2 C 1 2 2 fPCLK1 must be at least 2 MHz to achieve standard mode I C frequencies It must be at least 4 MHz to achieve fast mode I C f...

Страница 87: ...ble 48 SCL frequency fPCLK1 32 MHz VDD VDD_I2C 3 3 V 1 2 1 RP External pull up resistance fSCL I2 C speed 2 For speeds around 200 kHz the tolerance on the achieved speed is of 5 For other speed ranges...

Страница 88: ...Slave transmitter 12 3 3 The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle DuCy SCK ranging between 40 to 60 tr SCK 2 tf SCK 2 SPI clock rise a...

Страница 89: ...0 7VDD ai14134c SCK Input CPHA 0 MOSI INPUT MISO OUT PUT CPHA 0 MSB O UT M SB IN BIT6 OUT LSB IN LSB OUT CPOL 0 CPOL 1 BIT1 IN NSS input tSU NSS tc SCK th NSS ta SO tw SCKH tw SCKL tv SO th SO tr SCK...

Страница 90: ...interface is USB IF certified full speed Table 50 USB startup time Symbol Parameter Max Unit tSTARTUP 1 1 Guaranteed by design not tested in production USB transceiver startup time 1 s ai14136 SCK In...

Страница 91: ...2 V VCM 3 Differential common mode range Includes VDI range 0 8 2 5 VSE 3 Single ended receiver threshold 1 3 2 0 Output levels VOL 4 4 Tested in production Static output level low RL of 1 5 k to 3 6...

Страница 92: ...mbol Parameter Conditions Min Typ Max Unit VDDA Power supply 1 8 3 6 V VREF Positive reference voltage 2 4 V VDDA 3 6 V VREF must be below or equal to VDDA 1 8 1 VDDA V VREF Negative reference voltage...

Страница 93: ...source impedance 5 50 tlat Injection trigger conversion latency fADC 16 MHz 219 281 ns 3 5 4 5 1 fADC tlatr Regular trigger conversion latency fADC 16 MHz 156 219 ns 2 5 3 5 1 fADC tSTAB Power up tim...

Страница 94: ...4 6 5 LSB EO Offset error 2 4 EG Gain error 4 6 ED Differential linearity error 1 2 EL Integral linearity error 1 5 3 ET Total unadjusted error 1 8 V VDDA 2 4 V 1 8 V VREF 2 4 V fADC 4 MHz RAIN 50 TA...

Страница 95: ...1 LSBIDEAL 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line ET Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves E...

Страница 96: ...se as possible to the chip ADC clock Sampling n cycles Conversion 12 cycles Iref 300 A 700 A Table 56 RAIN max for fADC 16 MHz 1 Ts cycles Ts s RAIN max kOhm Multiplexed channels Direct channels 2 4 V...

Страница 97: ...and reference decoupling VREF not connected to VDDA 1 VREF and VREF inputs are available only on 100 pin packages Figure 30 Power supply and reference decoupling VREF connected to VDDA 1 VREF and VRE...

Страница 98: ...supply VDDA 3 3 V No load middle code 0x800 210 320 A No load worst code 0xF1C 320 520 A RL 2 Resistive load DAC output buffer ON 5 k CL 2 Capacitive load 50 pF RO Output impedance DAC output buffer...

Страница 99: ...F RL 5 k 7 12 s Update rate Max frequency for a correct DAC_OUT change 95 of final value with 1 LSB variation in the input code CL 50 pF RL 5 k 1 Msps tWAKEUP Wakeup time from off state setting the EN...

Страница 100: ...ration values Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C VDDA 3 V 0x1FF8 007A 0x1FF8 007B TS_CAL2 TS ADC raw data acquired at temperature...

Страница 101: ...IN Comparator 1 input voltage range 0 6 VDDA V tSTART Comparator startup time 7 10 s td Propagation delay 2 2 The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting inp...

Страница 102: ...e delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input the non inverting input set to the reference 1 V VDDA 2 7 V 1 8 3 5 2 7 V VDDA 3 6 V 2 5 6 td fast Propagatio...

Страница 103: ...nternal reference voltage 6 3 4 VLCD7 LCD internal reference voltage 7 3 55 Cext VLCD external capacitance 0 1 2 F ILCD 1 1 LCD enabled with 3 V internal step up active 1 8 duty 1 4 bias division rati...

Страница 104: ...s 7 1 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK s...

Страница 105: ...9 Rev 10 105 129 STM32L151x6 8 B STM32L152x6 8 B Package characteristics 128 Figure 32 LQFP100 14 x 14 mm 100 pin low profile quad flat package outline 1 Drawing is not to scale E 4 4 0 5 0 MM 3 4 0 C...

Страница 106: ...Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 15 800 16 000 16 200 0 6220 0 6299 0 63...

Страница 107: ...DocID17659 Rev 10 107 129 STM32L151x6 8 B STM32L152x6 8 B Package characteristics 128 Figure 33 Recommended footprint 1 Dimensions are in millimeters AI C...

Страница 108: ...characteristics STM32L151x6 8 B STM32L152x6 8 B 108 129 DocID17659 Rev 10 Figure 34 LQFP64 10 x 10 mm 64 pin low profile quad flat package outline 1 Drawing is not to scale 3 4 0 CCC B C 5 0 MM 4 4 0...

Страница 109: ...Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 11 800 12 000 12 200 0 4646 0 4724 0 4...

Страница 110: ...ge characteristics STM32L151x6 8 B STM32L152x6 8 B 110 129 DocID17659 Rev 10 Figure 36 LQFP48 7 x 7 mm 48 pin low profile quad flat package outline 1 Drawing is not to scale 6 0 4 4 CCC MM 5 0 B C E 3...

Страница 111: ...ax A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D...

Страница 112: ...line 1 Drawing is not to scale 2 All leads pads should also be soldered to the PCB to improve the lead pad solder joint life 3 There is an exposed die pad on the underside of the UFQFPN package It is...

Страница 113: ...rounded to 4 decimal digits Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 020 0 050 0 0000 0 0008 0 0020 D 6 900 7 000 7 100 0 2717 0 2756 0 2795 E 6 900 7 000 7 100 0 2...

Страница 114: ...ches 1 Min Typ Max Min Typ Max A 0 6 0 0236 A1 0 05 0 08 0 11 0 002 0 0031 0 0043 A2 0 4 0 45 0 5 0 0157 0 0177 0 0197 A3 0 08 0 13 0 18 0 0031 0 0051 0 0071 A4 0 27 0 32 0 37 0 0106 0 0126 0 0146 b 0...

Страница 115: ...s 128 eee 0 15 0 0059 fff 0 05 0 002 1 Values in inches are converted from mm and rounded to 4 decimal digits Table 67 UFBGA100 7 x 7 x 0 6 mm 0 5 mm pitch ultra thin fine pitch ball grid array packag...

Страница 116: ...pitch ball grid array package mechanical data Symbol millimeters inches 1 Min Typ Max Min Typ Max A 1 200 0 0472 A1 0 150 0 0059 A2 0 200 0 0079 A4 0 600 0 0236 b 0 250 0 300 0 350 0 0098 0 0118 0 013...

Страница 117: ...stics 128 eee 0 15 0 0059 fff 0 05 0 002 1 Values in inches are converted from mm and rounded to 4 decimal digits Table 68 TFBGA64 5 0x5 0x1 2 mm 0 5 mm pitch thin fine pitch ball grid array package m...

Страница 118: ...nded PCB design rules for pads 0 5 mm pitch BGA 1 Non solder mask defined NSMD pads are recommended 2 4 to 6 mils solder paste screen printing process Pitch 0 5 mm D pad 0 27 mm Dsm 0 35 mm typ depend...

Страница 119: ...is the maximum chip internal power PI O max represents the maximum power dissipation on output pins where PI O max VOL IOL VDD VOH IOH taking into account the actual VOL IOL and VOH IOH of the I Os at...

Страница 120: ...659 Rev 10 Figure 43 Thermal resistance 7 2 1 Reference document JESD51 2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air Available from www jedec org 7HPSH...

Страница 121: ...family STM32 ARM based 32 bit microcontroller Product type L Low power Device subfamily 151 Devices without LCD 152 Devices with LCD Pin count C 48 pins R 64 pins V 100 pins Flash memory size 6 32 Kb...

Страница 122: ...B0 and PC3 in Table 8 STM32L15xx6 8 B pin definitions Updated Table 14 Embedded reset and power control block characteristics Updated Table 16 Embedded internal reference voltage Added Table 53 ADC cl...

Страница 123: ...TRSTTEMPO VDD rising BOR enabled Table 17 Current consumption in Run mode code with data processing running from Flash on page 56 removed values for HSI clock source 16 MHz Range 3 Table 18 Current c...

Страница 124: ...d i2 as IHSE and updated max value updated max values for IDD HSE Table 29 LSE oscillator characteristics fLSE 32 768 kHz on page 71 updated max value for ILSE Table 30 HSI oscillator characteristics...

Страница 125: ...conditions and fHCLK Table 20 Current consumption in Low power run mode updated some temperature conditions added footnote 2 Table 21 Current consumption in Low power sleep mode updated some temperatu...

Страница 126: ...ed Table 66 UFQFPN48 7 x 7 mm 0 5 mm pitch ultra thin fine pitch quad flat no lead package mechanical data Updated Table 65 LQFP48 7 x 7 mm 48 pin low profile quad flat package mechanical data Added t...

Страница 127: ...This Section 6 3 5 Wakeup time from Low power mode was previously a paragraph in Section 6 3 4 Supply current characteristics Updated fHSE conditions in Table 17 Current consumption in Run mode code w...

Страница 128: ...e quad flat package mechanical data and Table 66 UFQFPN48 7 x 7 mm 0 5 mm pitch ultra thin fine pitch quad flat no lead package mechanical data Updated Figure 33 Recommended footprint Updated Figure 4...

Страница 129: ...ledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license expre...

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