Spectrum M2i.60xx, Руководство по оборудованию

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86 M2i.60xx / M2i.60xx-exp Manual
Internally generated sample rate Clock generation
Clock Mode Register
The selection of the different clock modes has to be done by the SPC_CLOCKMODE register. All available modes, can be read out by the
help of the SPC_AVAILCLOCKMODES register.
The different clock modes and all other related or required register settings are described on the following pages.
Internally generated sample rate
Standard internal sampling clock (PLL)
The internal sampling clock is generated in default mode by a PLL and dividers out of an internal precise 10 MHz frequency reference. You
can select the clock mode by the dedicated register shown in the table below:
In most cases the user does not have to care on how the desired sampling rate is generated by multiplying and dividing internally. You simply
write the desired sample rate to the according register shown in the table below and the driver makes all the necessary calculations. If you
want to make sure the sample rate has been set correctly you can also read out the register and the driver will give you back the sampling
rate that is matching your desired one best.
If a sampling rate is generated internally, you can additionally enable the clock output. The clock will be available on the external clock
connector and can be used to synchronize external equipment with the board.
Example on writing and reading internal sampling rate
Minimum internal sample rate
The minimum internal sample rate on all M2i cards is limited to 1 kHz and the maximum sample rate depends on the specific type of board.
The maximum sample rates for your type of card are shown in the tables below.
Register Value Direction Description
SPC_AVAILCLOCKMODES 20201 read Bitmask, in which all bits of the below mentioned clock modes are set, if available.
SPC_CLOCKMODE 20200 read/write Defines the used clock mode or reads out the actual selected one.
SPC_CM_INTPLL 1 Enables internal PLL with 10 MHz internal reference for sample clock generation
SPC_CM_QUARTZ1 2 Enables Quartz1 for sample clock generation
SPC_CM_QUARTZ2 4 Enables optional Quartz2 for sample clock generation
SPC_CM_EXTERNAL 8 Enables external clock input for direct sample clock generation
SPC_CM_EXTDIVIDER 16 Enables external clock input for divided sample clock generation
SPC_CM_EXTREFCLOCK 32 Enables internal PLL with external reference for sample clock generation
Register Value Direction Description
SPC_CLOCKMODE 20200 read/write Defines the used clock mode
SPC_CM_INTPLL 1 Enables internal PLL with 10 MHz internal reference for sample clock generation
Register Value Direction Description
SPC_SAMPLERATE 20000 write Defines the sample rate in Hz for internal sample rate generation.
read Read out the internal sample rate that is nearest matching to the desired one.
Register Value Direction Description
SPC_CLOCKOUT 20110 read/write Enables clock output on external clock connector.On A/D and D/A cards only possible with internal
clocking.
spcm_dwSetParam_i32 (hDrv, SPC_CLOCKMODE, SPC_CM_INTPLL); // Enables internal PLL mode
spcm_dwSetParam_i32 (hDrv, SPC_SAMPLERATE, 1000000); // Set internal sampling rate to 1 MHz
spcm_dwSetParam_i32 (hDrv, SPC_CLOCKOUT, 1); // enable the clock output of that 1 MHz clock
spcm_dwGetParam_i32 (hDrv, SPC_SAMPLERATE, &lSamplerate); // Read back the programmed sample rate and
printf („Sample rate = %d\n“, lSamplerate); // print it. Output should be „Sample rate = 1000000“