102
M2i.60xx / M2i.60xx-exp Manual
Generation Modes
Mode Gated Replay
Mode Gated Replay
The Gated Replay mode allows the data generation controlled by an exter-
nal or an internal gate signal. Data will only be replayed if the programmed
gate condition is true.
This chapter will explain all the necessary software register to set up the
card for Gated Replay properly.
The section on the allowed trigger modes deals with detailed description on
the different trigger events and the resulting gates.
Generation Modes
Standard Mode
Data will be replayed as long as the gate signal fulfils the programmed gate condition. At the end of the gate interval the replay will be
stopped and the card will pause until another gates signal appears. If loops (SPC_LOOPS) is set to 1 the card stops immediately as soon as
the total amount of data (SPC_MEMSIZE) has been replayed. In that case the last gate segment is ended by the expiring memory size counter
and not by the gate end signal. If loops is set to zero the Gated Replay mode will run in a continuous loop until explicitly stopped by user. If
the replay reaches the end of the programmed memory it will start again at the beginning with no gap in between. If setting loops to a number
larger than 1 this number of complete gates will be replayed and the card stopped afterwards automatically.
The table below shows the register for enabling Gated Sampling. For detailed information on how to setup and start the standard acquisition
mode please refer to the according chapter earlier in this manual.
The total number of samples to be replayed from the on-board memory in standard mode is defined by the SPC_MEMSIZE register.
Examples of Standard Gated Replay with the use of SPC_LOOPS parameter
To keep the diagram easy to read there’s no delay shown in here and there’s also only a very small number of samples shown. Any further
restrictions are described later in this chapter.
FIFO Mode
The Gated Replay in FIFO mode is similar to the Gated Replay in standard mode. The replay can either run until the user stops it by software
(infinite replay, loops = 0) or until a programmed number of gates has been played (loops = 1). The data is written continuously by the driver
and can be either online calculated or loaded from hard disk. The table below shows the dedicated register for enabling Gated Sampling in
FIFO mode. For detailed information how to setup and start the card in FIFO mode please refer to the according chapter earlier in this manual.
Register
Value
Direction
Description
SPC_CARDMODE
9500
read/write
Defines the used operating mode
SPC_REP_STD_GATE
400h
Enables Gated Sampling for standard acquisition.
Register
Value
Direction
Description
SPC_MEMSIZE
10000
read/write
Defines the total number of samples to be replayed.
SPC_LOOPS
10020
read/write
Defines the number of gates to be replayed
0
Replay will be infinite until the user stops it. When replay reaches the end of programmed memory it will start from the
beginning with no gap.
1
The complete memory is replayed once. The last gate segement is cut off when end of memory is reached.
2 … [4G - 1]
Defines the number of gate segments to be replayed.
Register
Value
Direction
Description
SPC_CARDMODE
9500
read/write
Defines the used operating mode
SPC_REP_FIFO_GATE
2000h
Enables Gated Replay with FIFO mode
